 mrg
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f2c45a230e
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Add new replica column test. Add more skip tests.
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2020-06-10 11:00:00 -07:00 |
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mrg
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10be2d08b5
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Full path to skip tests file
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2020-06-10 10:23:05 -07:00 |
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mrg
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5e3332453b
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Allow power pins to start on any layer besides m1
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2020-06-10 10:15:23 -07:00 |
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mrg
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c119e60e79
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Add more s8 skip tests
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2020-06-10 10:14:52 -07:00 |
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mrg
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d4fc88124a
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Rename dff_buf test
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2020-06-09 17:18:19 -07:00 |
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mrg
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064fe34edf
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Fix pinvbuf layers
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2020-06-09 17:16:35 -07:00 |
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mrg
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14782914b3
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Remove vertical pand gates
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2020-06-09 16:40:59 -07:00 |
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mrg
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e6babc301d
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Incrase space for pnand gates
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2020-06-09 16:34:15 -07:00 |
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mrg
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c6b875146d
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Use local skip file
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2020-06-09 16:33:59 -07:00 |
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mrg
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fd49d3ed6a
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Add tech specific skip tests for making new techs.
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2020-06-09 16:09:15 -07:00 |
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mrg
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580b0601b5
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Unskip 20_psram_1bank_4mux_1rw_1r_test
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2020-06-09 16:04:39 -07:00 |
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mrg
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a28e747a02
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Fix precharge offset. Move well rules to design class.
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2020-06-09 15:28:50 -07:00 |
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mrg
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148521c458
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Remove stdc layer
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2020-06-09 13:48:47 -07:00 |
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mrg
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157926960b
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Flip freepdk45 flop, dff_buf route layer change
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2020-06-09 13:48:16 -07:00 |
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mrg
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8c6d5b49be
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Consider diffusion spacing in active offset
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2020-06-09 13:09:52 -07:00 |
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mrg
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9cc36c6d3a
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Bus code converted to pins. Fix layers on control signal routes in bank.
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2020-06-08 11:01:14 -07:00 |
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mrg
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0837432d45
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Wordline route layers and (optional) via.
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2020-06-05 16:47:22 -07:00 |
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mrg
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5514996708
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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mrg
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00b51f5464
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PEP8 format replica_bitcell_array
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2020-06-05 13:49:32 -07:00 |
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mrg
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4fef632dce
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Fix syntax error
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2020-06-05 12:13:41 -07:00 |
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mrg
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a62b85a6b1
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Update mirroring in port_data for bitcell mirrored arrays
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2020-06-05 11:29:31 -07:00 |
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mrg
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2e7f9395f2
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Rename 05 test to 14
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2020-06-05 09:57:16 -07:00 |
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mrg
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68ffb94d2e
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Rename 05 test to 14
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2020-06-05 09:55:57 -07:00 |
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mrg
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fb3acae908
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PEP8 format testutils.
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2020-06-05 09:44:30 -07:00 |
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mrg
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e14deff3d1
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Fixed offset in port_data
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2020-06-04 16:03:39 -07:00 |
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mrg
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2fcecb7227
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Variable zjog. 512 port address test. s8 port address working.
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2020-06-04 16:01:32 -07:00 |
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mrg
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e06dc3810a
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Move precharge pin to bottom
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2020-06-04 12:12:19 -07:00 |
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mrg
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717188f85c
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Change L shape of rbl route
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2020-06-04 11:03:39 -07:00 |
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mrg
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7aafa43897
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Connect RBL to bottom of precharge cell
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2020-06-04 10:22:52 -07:00 |
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mrg
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249b5355ba
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Adjust rbl route
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2020-06-03 17:08:04 -07:00 |
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mrg
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77c95b28da
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Rename precharge test
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2020-06-03 16:39:46 -07:00 |
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mrg
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3927c62e32
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Undo extra space due to nwell spacing
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2020-06-03 16:39:33 -07:00 |
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mrg
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b2b7e7800b
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Undo same bitline pitch
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2020-06-03 16:39:05 -07:00 |
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mrg
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4183638f03
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Align precharge bitlines with col mux
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2020-06-03 16:05:57 -07:00 |
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mrg
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4bc1e9a026
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Fix the bitline spacing in the column mux to a constant.
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2020-06-03 15:47:03 -07:00 |
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mrg
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3b1fe26d25
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Spacing between decoder and driver for s8
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2020-06-03 14:33:30 -07:00 |
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mrg
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e93f3f1d2e
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Add 1rw_1r tests
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2020-06-03 14:30:15 -07:00 |
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mrg
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b78166c044
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Merge branch 'dev' into tech_migration
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2020-06-03 14:08:22 -07:00 |
|
 Joey Kunzler
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7a602b75a4
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keep dev routing changes to hierarchy_layout
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2020-06-03 12:54:15 -07:00 |
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Joey Kunzler
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6430aad857
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Merge branch 'dev' into s8_update
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2020-06-03 11:53:33 -07:00 |
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mrg
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38f5e8b865
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Add col mux tests for multiport
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2020-06-03 10:01:02 -07:00 |
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mrg
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34209dac3d
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A port option for correct mirroring in port_data.
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2020-06-02 16:50:07 -07:00 |
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Joey Kunzler
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84021c9ccb
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merge conflict 2 - port data
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2020-06-02 16:32:08 -07:00 |
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Joey Kunzler
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001bf1b827
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merge conflict - port data
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2020-06-02 14:15:39 -07:00 |
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mrg
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fce8e878b9
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Add port to col mux and simplify route with computation to fix mirror bug.
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2020-06-02 13:57:41 -07:00 |
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mrg
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fdf51c5a00
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Add port option to precharge array
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2020-06-02 11:44:22 -07:00 |
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mrg
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f1b7b91b1a
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Use non-channel route for s8 port_data
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2020-06-02 11:43:57 -07:00 |
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mrg
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45b0601e4b
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Fix via directions in s8 col mux
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2020-06-02 11:43:31 -07:00 |
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mrg
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a1c7474f80
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Revert to channel route of bitlines
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2020-06-02 10:08:53 -07:00 |
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mrg
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620604603c
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Fixed offset jogs
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2020-06-02 10:08:37 -07:00 |
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