OpenRAM/compiler
mrg b78166c044 Merge branch 'dev' into tech_migration 2020-06-03 14:08:22 -07:00
..
base keep dev routing changes to hierarchy_layout 2020-06-03 12:54:15 -07:00
bitcells merge conflict - port data 2020-06-02 14:15:39 -07:00
characterizer Merge remote-tracking branch 'public/dev' into dev 2020-04-22 09:28:25 -07:00
custom Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
datasheet
drc PEP8 cleanup 2020-04-15 11:24:28 -07:00
example_configs revert example scn4m to non netlist only 2020-02-09 23:52:11 -08:00
gdsMill added purposes to addText(), removed reference to specific tech from gdsMill 2020-02-19 16:26:52 -08:00
modules Merge branch 'dev' into s8_update 2020-06-03 11:53:33 -07:00
pgates merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
router Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
sram Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
tests Merge branch 'dev' into tech_migration 2020-06-03 14:08:22 -07:00
verify Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
Makefile
debug.py Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
gen_stimulus.py
globals.py Merge remote-tracking branch 'public/dev' into dev 2020-04-22 09:28:25 -07:00
openram.py Only setup bitcell when running top-level OpenRAM 2019-11-26 13:54:37 -08:00
options.py merge conflict - port data 2020-06-02 14:15:39 -07:00
run_profile.sh
sram_factory.py SRAM factory uses default name for first instance even if it has arguments. 2020-06-01 16:46:22 -07:00
view_profile.py