mrg 4bc1e9a026 Fix the bitline spacing in the column mux to a constant.

2020-06-03 15:47:03 -07:00

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base

keep dev routing changes to hierarchy_layout

2020-06-03 12:54:15 -07:00

bitcells

merge conflict - port data

2020-06-02 14:15:39 -07:00

characterizer

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custom

Hard cells can accept height parameter too.

2020-06-01 16:46:00 -07:00

datasheet

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drc

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example_configs

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gdsMill

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modules

Spacing between decoder and driver for s8

2020-06-03 14:33:30 -07:00

pgates

Fix the bitline spacing in the column mux to a constant.

2020-06-03 15:47:03 -07:00

router

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sram

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tests

Fix the bitline spacing in the column mux to a constant.

2020-06-03 15:47:03 -07:00

verify

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debug.py

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gen_stimulus.py

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globals.py

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Makefile

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openram.py

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options.py

merge conflict - port data

2020-06-02 14:15:39 -07:00

run_profile.sh

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sram_factory.py

SRAM factory uses default name for first instance even if it has arguments.

2020-06-01 16:46:22 -07:00

view_profile.py

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