 Aditi Sinha
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5c50cf234b
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Fixed lvs errors for spare columns
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2020-05-09 07:56:19 +00:00 |
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Aditi Sinha
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e30938fb66
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Spare columns working at bank level
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2020-05-03 15:23:30 +00:00 |
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Aditi Sinha
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2498ff07ea
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Merge branch 'dev' into bisr
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2020-05-02 07:48:35 +00:00 |
|
 Joey Kunzler
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1b6634bb97
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port data routing fix
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2020-04-29 15:48:15 -07:00 |
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Joey Kunzler
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0bae652be9
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fix merge conflicts
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2020-04-23 11:51:46 -07:00 |
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Joey Kunzler
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fed1c0bbe1
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s8 col mux array
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2020-04-22 16:22:34 -07:00 |
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 mrg
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32576fb62c
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Convert wordline driver to pand2 rather than pnand2+pdriver
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2020-04-22 13:27:50 -07:00 |
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mrg
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f1c1adc9bd
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Simplify supply contacts in delay chain.
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2020-04-21 16:12:54 -07:00 |
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mrg
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0f6998a1c5
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PEP8 cleanup
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2020-04-21 15:36:38 -07:00 |
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mrg
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cd66ddb37c
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Add supply rails to dff array. PEP8 cleanup.
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2020-04-21 15:21:29 -07:00 |
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mrg
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f6135f3471
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PEP8 formatting
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2020-04-20 16:38:30 -07:00 |
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mrg
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7995451cbb
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PEP8 formatting
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2020-04-20 14:45:18 -07:00 |
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mrg
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7f65176908
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Configured bitline directions into prot_data
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2020-04-20 14:23:40 -07:00 |
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mrg
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843e9414df
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Parameterize vdd and gnd pin in write driver array.
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2020-04-16 11:28:35 -07:00 |
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mrg
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770533e7b1
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Parameterize vdd and gnd pin in sense amp array.
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2020-04-16 11:27:26 -07:00 |
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mrg
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9d2902de9e
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Conditional well spacing
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2020-04-15 15:55:49 -07:00 |
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mrg
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e95c97d7a5
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PEP8 cleanup
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2020-04-15 14:29:43 -07:00 |
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mrg
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331a4f4606
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Fix wire width bug in short jogs. PEP8 cleanup.
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2020-04-15 09:48:42 -07:00 |
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mrg
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0941ebc3da
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Fix well spacing issue
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2020-04-14 14:08:07 -07:00 |
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mrg
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32d190b8b1
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Jog connection on M1 for bank select.
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2020-04-14 12:15:56 -07:00 |
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mrg
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43dcf675a1
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Move pnand outputs to M1. Debug hierarchical decoder multirow.
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2020-04-14 10:52:25 -07:00 |
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Aditi Sinha
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2661a42726
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changes to support spare columns
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2020-04-14 03:09:10 +00:00 |
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mrg
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2e67d44cd7
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First pass of multiple bitcells per decoder row
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2020-04-10 13:29:41 -07:00 |
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mrg
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7888e54fc4
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Remove dynamic bitcell multiple detection.
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
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2020-04-09 11:38:18 -07:00 |
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mrg
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8a55c223df
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Use single height for netlist_only mode
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2020-04-09 09:48:54 -07:00 |
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mrg
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58fbc5351a
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Change rows to outputs in hierarchical decoder
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2020-04-08 17:05:16 -07:00 |
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mrg
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0c27942bb2
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Dynamically try and DRC decoder for height
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2020-04-08 16:45:28 -07:00 |
|
 Jesse Cirimelli-Low
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b59c789dec
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remove whitespace
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2020-04-05 03:58:26 -07:00 |
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Jesse Cirimelli-Low
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8b33cb519f
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Merge branch 'dev' into custom_mod
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2020-04-03 17:05:56 -07:00 |
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mrg
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2850b9efb5
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Don't force check in lib characterization. PEP8 formatting.
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2020-04-02 12:52:42 -07:00 |
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mrg
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5349323acd
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PEP8 cleanup. DRC/LVS returns errors.
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2020-04-02 09:47:39 -07:00 |
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mrg
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a9d3548be1
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Refactor drc/lvs error output
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2020-04-01 15:54:06 -07:00 |
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Jesse Cirimelli-Low
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cdf0315a90
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Merge branch 'dev' into custom_mod
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2020-04-01 15:35:33 -07:00 |
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mrg
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7956b63d9f
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Add licon option to precharge
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2020-04-01 11:26:45 -07:00 |
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mrg
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d916322b74
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PEP8 updates
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2020-03-31 10:15:46 -07:00 |
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Joey Kunzler
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b0d2946c80
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update to sense amp and write driver modules
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2020-03-30 20:00:32 -07:00 |
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Jesse Cirimelli-Low
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341bde7a48
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Merge branch 'dev' into custom_mod
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2020-03-26 02:40:37 -07:00 |
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Aditi Sinha
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b75eeb7688
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Merge branch 'dev' into bisr
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2020-03-22 21:58:04 +00:00 |
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mrg
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c5a1be703c
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Rotate via and PEP8 formatting
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2020-03-06 13:39:46 -08:00 |
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mrg
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23501c7b35
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Convert pnand+pinv to pand in decoders.
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2020-03-06 13:26:40 -08:00 |
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mrg
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1a2efd77ad
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Move rbl route away from bitcell array
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2020-03-06 09:48:20 -08:00 |
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mrg
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ee18f61cbf
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Route RBL to edge of bank.
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2020-03-06 09:03:52 -08:00 |
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mrg
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ad98137cd4
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Merge branch 'dev' into tech_migration
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2020-03-05 14:18:06 -08:00 |
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mrg
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9c1f0657dd
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PEP8 Formatting
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2020-03-05 11:58:36 -08:00 |
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mrg
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7adeef6c9e
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PEP8 Formatting
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2020-03-05 10:21:18 -08:00 |
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mrg
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287a31f598
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Precharge updates.
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
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2020-03-04 17:39:11 -08:00 |
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Joey Kunzler
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d7529ce526
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Vdd/gnd via stacks now use perferred directions, added cell property to override
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2020-03-04 17:05:19 -08:00 |
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mrg
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7ba9e09e12
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Incomplete precharge layer decoupling
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2020-03-04 22:23:05 +00:00 |
|
 Jesse Cirimelli-Low
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f62016ad9f
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revert dff_buf for no body contact
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2020-03-03 12:40:08 +00:00 |
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mrg
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bb2305d56a
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PEP8 format fixes
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2020-02-28 18:24:39 +00:00 |
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