Jesse Cirimelli-Low f62016ad9f revert dff_buf for no body contact

2020-03-03 12:40:08 +00:00

..

bank_select.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

bank.py

bank: Connect instances by their individual bl/br names

2020-02-12 15:00:50 +01:00

bitcell_array.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

bitcell_base_array.py

replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names

2020-02-12 15:37:47 +01:00

control_logic.py

merge custom cell and module properties

2020-02-12 04:09:40 +00:00

delay_chain.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dff_array.py

add custom module file, make dff clk pin dynamic

2020-02-04 23:35:06 -08:00

dff_buf_array.py

Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev

2020-02-12 06:54:03 +00:00

dff_buf.py

revert dff_buf for no body contact

2020-03-03 12:40:08 +00:00

dff_inv_array.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dff_inv.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dff.py

merge custom cell and module properties

2020-02-12 04:09:40 +00:00

dummy_array.py

Fix base bitcell syntax error. Remove some unused imports.

2020-01-30 01:58:30 +00:00

hierarchical_decoder.py

Nwell fixes in pgates.

2020-02-06 16:20:09 +00:00

hierarchical_predecode2x4.py

Removed all unused analytical delay functions.

2019-08-06 17:09:25 -07:00

hierarchical_predecode3x8.py

Removed all unused analytical delay functions.

2019-08-06 17:09:25 -07:00

hierarchical_predecode.py

Nwell fixes in pgates.

2020-02-06 16:20:09 +00:00

module_type.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

multibank.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

port_address.py

Add separate well design rules.

2020-01-23 19:43:41 +00:00

port_data.py

port_data: Each submodule now specifies their bl/br names

2020-02-12 15:00:50 +01:00

precharge_array.py

port_data: Each submodule now specifies their bl/br names

2020-02-12 15:00:50 +01:00

replica_bitcell_array.py

replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names

2020-02-12 15:37:47 +01:00

replica_column.py

Bitcell arrays: Allow mirroring on the y axis

2020-01-28 15:51:21 +01:00

sense_amp_array.py

port_data: Each submodule now specifies their bl/br names

2020-02-12 15:00:50 +01:00

sense_amp.py

port_data: Each submodule now specifies their bl/br names

2020-02-12 15:00:50 +01:00

single_level_column_mux_array.py

port_data: Each submodule now specifies their bl/br names

2020-02-12 15:00:50 +01:00

tri_gate_array.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

tri_gate.py

Made all cin function relate to farads and all input_load relate to relative units.

2019-08-08 01:57:04 -07:00

wordline_driver.py

Pgates are 8 M1 high by default. Port data is bitcell height.

2020-01-30 03:34:04 +00:00

write_driver_array.py

port_data: Each submodule now specifies their bl/br names

2020-02-12 15:00:50 +01:00

write_driver.py

port_data: Each submodule now specifies their bl/br names

2020-02-12 15:00:50 +01:00

write_mask_and_array.py

Move write mask vias to center to avoid data pins.

2019-12-20 11:48:27 -08:00