before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
each module should be able to state how their bl/br lines are named. Here we
always connect port_data with the bitcell_array, so port_data needs function
that return the names of bl/br.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
since the bitlines alternate in the bitcell array we also need to mirror
the port_data elements.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
since the bitlines alternate in the bitcell array we also need to mirror
the port_data elements.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
this allows for bitcells that need to be mirrored on the y axis, like
thin cells. However, the portdata elements also need to be mirrored on
the y axis. Otherwise the router will fail horribly when connecting
bitlines.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
this is technology specific database to store data about the custom
design cells. For now it only contains on which axis the bitcells are
mirrored. This is a first step to support thin cells that need to be
mirrored on the x and y axis.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
a lot of functions of dummy- and bitcell-array are either copy-pasted or
have just slight differences. Merge all of those into an abstract base
class such that we don't have too much duplicate code.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
modules overridden by the user are the highest priority, then modules
overridden by the technology. If nothing is overriden, use the defaults
from OPTS (if they exist) or use the requested module_type.
This fixes that custom tech_modules could not be used, if they had a default in
OPTS even if the latter was not overridden by the user.
We don't need extra defaults in the tech_modules, as we now only use them,
if they have been overridden by the tech_module.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
this removes hard coded values from the module instatiations. It also allows
users to override certain modules with their custom cells.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Comment about write driver size for write through to work, but
disable write through in functional simulation.
Provide warning in Verilog about write throughs.
Hunter Nichols
Bastian Koppelmann
Jesse Cirimelli-Low
mrg
Aditi Sinha