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OpenRAM
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4617 Commits

Author SHA1 Message Date
Matt Guthaus ea04900acb
Merge pull request #121 from erendo/fix_verilog 
Fix Verilog
 2021-08-30 09:33:35 -07:00
erendo e9b370bf21 Fix write masks in Verilog 2021-08-29 00:31:32 +03:00
Hunter Nichols 680d7b5d93 Added special RC delay functions for the bitline and sense amp to match CACTI. Contains temporary parameters which need to be defined. 2021-08-25 16:12:05 -07:00
Hunter Nichols de2dae4030 Changed unit capacitance from CACTI estimation to PTM estimation. 2021-08-25 15:23:12 -07:00
mrg 6f4d9f17af v1.1.18 2021-08-18 11:30:00 -07:00
mrg ba97fa9f85 Merge branch 'stable' into dev 2021-08-18 11:28:16 -07:00
Hunter Nichols 12c03ddd9f Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti. 2021-08-16 22:58:26 -07:00
Hunter Nichols b3500982ca Fixed issue with wire resistance in total resistance equations for cacti. Fixed issue with sense amp resistance values. 2021-08-04 16:10:27 -07:00
Hunter Nichols 134bf573ec Removed windows EOL characters. 2021-08-04 16:09:04 -07:00
mrg c117238fa7 Initial klayout DRC/LVS options 2021-08-03 14:41:09 -07:00
Hunter Nichols b44f840814 Changed delay calculation to include wire resistance and wire capacitance. Added bitline r and c values. 2021-08-01 19:25:54 -07:00
Hunter Nichols 1b89533d7b Added unit r and c values with m2 minwidth incorporated to match CACTI params 2021-08-01 00:23:59 -07:00
biarmic 85955ce298 Fix addr flop in Verilog 2021-07-30 12:22:55 +03:00
mrg 0589a35f73 Merge branch 'dev' into stable 2021-07-29 11:42:15 -07:00
mrg e88f927e01 v1.1.17 2021-07-29 11:41:41 -07:00
mrg aa0e221863 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-07-28 12:07:05 -07:00
mrg 90a4ad4d75 Update size of 30 config tests to 2 bits. 2021-07-28 12:05:31 -07:00
mrg e391186581 Update klayout tech files 2021-07-28 11:42:56 -07:00
mrg 9694237dba Flip MSB and LSB in lib file due to bug report 2021-07-28 08:12:33 -07:00
Hunter Nichols 54cbef1aff Replaced cacti tech params with already existing params. Added an existence check in design_rules. 2021-07-27 14:31:22 -07:00
Hunter Nichols 1e08005639 Merge branch 'dev' into cacti_model 2021-07-26 14:35:47 -07:00
Hunter Nichols 3e0a49e58d Added options for the model type in timing graph (cacti or elmore) 2021-07-25 22:28:23 -07:00
Hunter Nichols 5ad86538d4 Renamed graph_util to timing_graph to match the module name 2021-07-25 20:21:54 -07:00
Hunter Nichols 7fc4469b97 Converted input load to Farads for cacti module to fit other units. 2021-07-25 17:22:03 -07:00
Hunter Nichols 7dd9023ce4 Uncommented horowitz delay function. 2021-07-21 15:02:39 -07:00
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files. 2021-07-21 14:59:02 -07:00
Hunter Nichols 1acc10e9d5 Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions. 2021-07-21 12:24:08 -07:00
Hunter Nichols a312639ef8 Added tech params for on-resistance and load capacitances 2021-07-21 11:00:32 -07:00
Hunter Nichols f6924b7cc2 Removed unusued inputs in drain_c function 2021-07-20 11:33:18 -07:00
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
Hunter Nichols 2c9f755a73 Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
Hunter Nichols e9bea4f0b6 Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions. 2021-07-12 13:02:22 -07:00
mrg cce1305da3 Add technology parameter for library prefix during uniquification of GDS 2021-07-12 11:01:51 -07:00
mrg bd64912977 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-07-09 12:31:48 -07:00
mrg 0d6d707315 Reset write_size to none when it is the same as data word width 2021-07-09 12:31:35 -07:00
Jesse Cirimelli-Low 1a7adcfdad fix vnb and vpb routing in rba 2021-07-08 18:31:55 -07:00
Hunter Nichols c1efa2de59 Added delay function for cacti, moved cacti related delay functions to hierarchy_spice, and trimmed the functions to remove irrelevant options for OpenRAM. 2021-07-07 13:22:30 -07:00
Jesse Cirimelli-Low b5daa51a6c don't use hard coded purpose numbers 2021-07-01 17:31:01 -07:00
mrg 0464ec3f16 Skip 50 tests 2021-07-01 16:38:39 -07:00
mrg 55f09d00a4 Make replica_column sky130 friendly 2021-07-01 16:15:13 -07:00
mrg 879f945aa7 Add risc5 functional tests 2021-07-01 16:13:14 -07:00
Jesse Cirimelli-Low 8a0e3e5caf Merge remote-tracking branch 'origin/dev' into dev 2021-07-01 15:22:29 -07:00
Jesse Cirimelli-Low e280efda7b don't copy pwell pin onto nwell 2021-07-01 15:19:59 -07:00
mrg 6be24d4c6c Only 25 cycles 2021-07-01 12:50:20 -07:00
mrg 3d2b192682 Add conditional spare row/col to a couple unit tests 2021-07-01 12:49:30 -07:00
mrg 2711093442 Improve signal debug output 2021-07-01 12:47:17 -07:00
mrg bbdc728ac5 Edits to functional simulation. 
Use correct .TRAN with max timestep.
Seed functional sim with a 3 writes to start for more read addresses.
Move formatting code to simulation module to share.
 2021-07-01 09:59:13 -07:00
Hunter Nichols 8c48520de6 Added cacti-like model and adapted several functions from cacti into python. 2021-06-30 15:50:54 -07:00
Jesse Cirimelli-Low 278c40f4b7 Merge remote-tracking branch 'origin/dev' into dev 2021-06-30 05:24:23 -07:00
Jesse Cirimelli-Low c9b3f4772e fix bias correspondence points 2021-06-30 05:21:39 -07:00