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OpenRAM
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4617 Commits

Author SHA1 Message Date
Bugra Onal d53353b5be Merge branch 'dev' into char 2023-07-19 12:06:34 -07:00
Bugra Onal 9fa25690ce Added pins for spare_cols 2023-07-19 11:35:09 -07:00
vlsida-bot 5dbc22091c Bump version: 1.2.21 -> 1.2.22 2023-07-19 00:29:46 +00:00
mrg 54c2710aea Add OPENRAM_TMP back to macro Makefiles to save results. 2023-07-18 15:45:15 -07:00
vlsida-bot 3ef61a298f Bump version: 1.2.20 -> 1.2.21 2023-07-18 22:18:17 +00:00
mrg 699f7b311e Add DIRS back to Makefile so we can use targets without .ok extension. 2023-07-18 10:58:04 -07:00
mrg 148d80531e Add fetch to remove error when re-installing PDK cells. 2023-07-18 10:48:22 -07:00
vlsida-bot 7bd312faff Bump version: 1.2.19 -> 1.2.20 2023-07-18 00:59:02 +00:00
Sam Crow b1b6886bac Merge branch 'delay_ctrl' into dev 2023-07-17 16:05:57 -07:00
Bugra Onal 833d4c12a6 skip 30_tests for sky130 2023-07-11 10:15:26 -07:00
vlsida-bot 37b7de4653 Bump version: 1.2.18 -> 1.2.19 2023-07-11 00:25:28 +00:00
Sam Crow 89d8441108 Merge branch 'dev' into delay_ctrl 2023-07-10 14:31:26 -07:00
Samuel Crow 042a3ed14f
skip non-scmos delay control tests for now 2023-07-10 14:28:19 -07:00
Bugra Onal ed0c93ba55 Only add drc errors from compiler 2023-07-10 14:05:44 -07:00
Bugra Onal eddc9af45b Merge branch 'dev' into char 2023-07-10 13:55:50 -07:00
Sam Crow 4e649aad6b fix typo bug in spice comments code 2023-07-10 13:21:24 -07:00
Jesse Cirimelli-Low 513c7e9f71 update sram library commit 2023-07-10 13:12:13 -07:00
Bugra Onal 0ad619f04c Added bl, sen and cell format options 2023-07-10 12:32:58 -07:00
Bugra Onal 7220e0a483 sim_exe will be found everytime with func and char 2023-07-07 12:39:19 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 468c972acb add optional guard band to delay chain sizing 2023-07-05 16:34:42 -07:00
Bugra Onal 071670bef0 Removed import global 2023-07-05 14:29:51 -07:00
Sam Crow d65ccfcc95 fix column mux without rbl start_bit to 0 2023-07-05 13:17:46 -07:00
Sam Crow b4a9784835 model vth delay swing delay 2023-07-05 12:17:48 -07:00
Sam Crow 5235cf9667 model p_en and wl_en delays in delay chain sizing 2023-07-03 17:02:11 -07:00
Sam Crow e1865083d7 incomplete work on improved delay modeling 2023-06-29 14:44:42 -07:00
Sam Crow 91694fdae3 add fixme note for unit conversion 2023-06-28 14:05:42 -07:00
vlsida-bot 3620d56790 Bump version: 1.2.17 -> 1.2.18 2023-06-27 00:22:04 +00:00
Jesse Cirimelli-Low 14f8008c4f
Update index.md 
fix typo in index.md
 2023-06-26 15:37:42 -07:00
Sam Crow 28ea93bd0a convert 1-indexing to 0-indexing 2023-06-25 11:03:10 -07:00
Sam Crow 006eacd6d0 add pinout message output 2023-06-25 10:46:58 -07:00
vlsida-bot 3cd3a63419 Bump version: 1.2.16 -> 1.2.17 2023-06-24 16:55:37 +00:00
Eren Dogan 3ada5347eb Set shell in the Makefile 2023-06-23 20:59:28 -07:00
Eren Dogan 92c8770472 Fix publications 2023-06-23 20:38:49 -07:00
Sam Crow 8992c0fb68 first approximation of delay values 2023-06-20 16:22:03 -07:00
Sam Crow dbc9de6c9a implement relationship between delay pinouts 2023-06-14 17:10:07 -07:00
vlsida-bot 542df33878 Bump version: 1.2.15 -> 1.2.16 2023-06-14 23:14:13 +00:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia b9e61f346a Merge branch 'dev' into openROM-verilogoutput 
To test recent changes with ROM verilog output
 2023-06-14 12:26:07 -07:00
Gary Mejia a3284e8b47 Fixed module from writing syntax issues 2023-06-13 17:30:38 -07:00
Sam Crow bf516a927d add skeleton for delay chain sizing 2023-06-13 13:44:32 -07:00
Sam Crow fee90283b9 add spacing and a comment 2023-06-12 16:56:44 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Sam Crow 96a1d400fa add single port bank test for norbl 2023-06-12 12:50:50 -07:00
Sam Crow 266bcd9cf2 consolidate failing xyce delay tests to one in skip list 2023-06-11 14:52:26 -07:00
Sam Crow 854bff9dce add norbl bank tests to sky130 skipped tests 2023-06-08 13:22:12 -07:00
Sam Crow 7048a072e2 add local/global array sky130 skipped tests 2023-06-08 13:16:27 -07:00
Sam Crow 44ed72b50d add has_rbl=True arg to tests 2023-06-08 13:10:03 -07:00
Sam Crow ce622952ef route rbl conditionally 2023-06-08 12:36:31 -07:00
Sam Crow a51b71d460 update copyright 2023-06-08 12:36:12 -07:00