2558 Commits

Author	SHA1	Message	Date
jcirimel	d40c3588ed	no wl for col end	2020-10-08 03:34:16 -07:00
jcirimel	4a1a7e637e	merge in dev	2020-10-07 11:54:07 -07:00
mrg	483f6b187c	RBL driver supply location differs for sky130 and other techs	2020-10-06 16:47:32 -07:00
mrg	c2629edc1b	Allow 16-way column mux	2020-10-06 16:27:02 -07:00
mrg	27d921d2db	Fix run-time bug for duplicate instance check	2020-10-06 16:26:35 -07:00
mrg	ba432669a1	Add various riscv examples	2020-10-06 16:25:44 -07:00
jcirimel	13e2a9f5f7	fix missed self.left_rbl refactor	2020-10-06 05:11:15 -07:00
jcirimel	888646cdf9	merge in wlbuf and begin work on 32kb memory	2020-10-06 05:03:59 -07:00
mrg	a145a37cf7	PEP8 fixes in regress.py	2020-10-05 15:56:12 -07:00
mrg	cb35c0aff4	Add command line -j option for number of threads.	2020-10-05 15:49:00 -07:00
mrg	da83824a70	Merge branch 'wlbuffer' into dev	2020-10-05 15:33:54 -07:00
mrg	c4952ca8be	Skip full sram pex test too slow	2020-10-05 13:51:20 -07:00
mrg	9fe6358569	Change .spinit to .spiceinit	2020-10-05 13:50:04 -07:00
jcirimel	5246d0a93b	track s8 customs modules	2020-10-05 12:10:44 -07:00
mrg	4a58f09c1c	Use 4x16 decoder with dual port bitcell in tests.	2020-10-05 10:52:56 -07:00
mrg	c06b02e6fc	Rename single_level_column_mux to just column_mux	2020-10-05 08:56:51 -07:00
mrg	f8146e3f69	Add decoder4x16	2020-10-02 15:52:09 -07:00
mrg	64cc620440	Add sram pex test	2020-10-02 14:55:10 -07:00
mrg	1fc4040607	Add pand4 and pnand4	2020-10-02 14:54:12 -07:00
mrg	a62b82128c	Skip riscv func test because too slow	2020-10-02 13:33:58 -07:00
mrg	1e24b780bb	Initial pex sram test.	2020-10-02 13:32:52 -07:00
mrg	b32c123dab	PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.	2020-10-01 11:10:18 -07:00
mrg	18c8ad265e	Unique name for sram channel routes	2020-10-01 09:55:34 -07:00
mrg	aaa36bf5cf	Default to 2 threads only	2020-10-01 09:55:17 -07:00
mrg	d315ff18e5	Add num_threads to options. PEP8 cleanup.	2020-10-01 08:07:03 -07:00
mrg	b81cdab0d6	Use unique instance names for channel routes.	2020-10-01 07:43:06 -07:00
mrg	8ce23d7f17	Provide unique WL driver instance name	2020-10-01 07:17:32 -07:00
mrg	bd125e2ed3	Check for duplicate instance names.	2020-10-01 07:17:16 -07:00
Matt Guthaus	2b475670f7	Check for failed result in functional simulation	2020-09-30 12:40:07 -07:00
Matt Guthaus	112d57d90a	Enable riscv tests	2020-09-30 12:39:40 -07:00
mrg	f4e6a8895b	Update riscv unit test	2020-09-30 08:50:58 -07:00
jcirimel	7cbf456a4f	sky130 rba done	2020-09-30 07:34:05 -07:00
mrg	b147e8485c	PEP8 formatting	2020-09-29 16:52:27 -07:00
mrg	066570bfeb	Fix length of write driver	2020-09-29 16:51:55 -07:00
mrg	8e908f016e	PEP8 formatting	2020-09-29 13:43:59 -07:00
mrg	bca69b24e3	Optional number of functional cycles	2020-09-29 13:43:54 -07:00
mrg	54890a8d77	Add new golden data	2020-09-29 13:43:34 -07:00
mrg	449a4c2660	Exclude bitcells in other local areas not of interest	2020-09-29 12:15:42 -07:00
mrg	0c280e062a	Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case.	2020-09-29 11:35:58 -07:00
mrg	4b5bbe755f	PEP8 cleanup. Fix cur_slew bug.	2020-09-29 11:13:58 -07:00
mrg	9032bb9869	Add global wordline delay test	2020-09-29 10:28:57 -07:00
mrg	d7e2340e62	Lots of PEP8 cleanup. Refactor path graph to simulation class.	2020-09-29 10:26:31 -07:00
mrg	1eb8798bb6	Add global functional test	2020-09-28 16:12:09 -07:00
mrg	b2dab486fc	Add draft of path exclusion calls	2020-09-28 16:05:21 -07:00
mrg	4a987bef9a	Merge branch 'wlbuffer' into dev	2020-09-28 15:51:45 -07:00
mrg	159c04a25d	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev	2020-09-28 15:51:35 -07:00
mrg	70c90ca7fb	Replica bitcell array bbox to include unused WL gnd pins.	2020-09-28 14:49:33 -07:00
mrg	9c6d8d7aed	Zjob to bottom.	2020-09-28 13:16:03 -07:00
mrg	5ab0d01779	Remove zjog and go with L shape.	2020-09-28 12:48:37 -07:00
mrg	d65eb16513	Zjog the WL enable. Min driver is 1.	2020-09-28 12:24:55 -07:00