 mrg
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159c04a25d
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-09-28 15:51:35 -07:00 |
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mrg
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70c90ca7fb
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Replica bitcell array bbox to include unused WL gnd pins.
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2020-09-28 14:49:33 -07:00 |
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mrg
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9c6d8d7aed
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Zjob to bottom.
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2020-09-28 13:16:03 -07:00 |
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mrg
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5ab0d01779
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Remove zjog and go with L shape.
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2020-09-28 12:48:37 -07:00 |
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mrg
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d65eb16513
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Zjog the WL enable. Min driver is 1.
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2020-09-28 12:24:55 -07:00 |
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mrg
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6f06bb9dd5
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Create sized RBL WL driver in port_address
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2020-09-28 11:30:21 -07:00 |
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mrg
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88731ccd8e
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Fix rounding error for wmask with various word_size
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2020-09-28 09:53:01 -07:00 |
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 jcirimel
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3dd72cdeac
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progress with rba pin mismatch
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2020-09-23 08:37:32 -07:00 |
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jcirimel
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17e6e5eb16
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row end col done
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2020-09-23 08:02:56 -07:00 |
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jcirimel
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5c263e0001
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rep col done w/o power pins
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2020-09-23 06:24:52 -07:00 |
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jcirimel
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7afe3ea52c
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replica col arrangement done
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2020-09-23 04:51:09 -07:00 |
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jcirimel
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efdc171b14
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make split wl specific to each port
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2020-09-23 00:08:34 -07:00 |
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jcirimel
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fb6a665514
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removed references to technology name
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2020-09-22 18:33:03 -07:00 |
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jcirimel
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de33ab3761
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fix single port bitcell pattern
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2020-09-22 15:08:53 -07:00 |
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mrg
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c7d32089f3
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Create RBL wordline buffer with correct polarity.
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2020-09-17 14:45:49 -07:00 |
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jcirimel
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559dfbc7a6
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single port bitcell array done
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2020-09-16 05:46:14 -07:00 |
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mrg
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e7ad22ff69
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Separate WL via from bitell array to avoid grounded WLs
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2020-09-15 13:38:28 -07:00 |
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mrg
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5e94d76127
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Make global bitline only as wide as needed rather than whole array
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2020-09-15 13:24:38 -07:00 |
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mrg
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aff3cd2aab
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Update length of control bus
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2020-09-15 09:49:00 -07:00 |
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jcirimel
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d22164bd48
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single port progess
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2020-09-14 18:11:38 -07:00 |
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mrg
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f25b6ffa61
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Make control bus height of port data
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2020-09-14 15:42:17 -07:00 |
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mrg
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7b24d1f012
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Use pins for write_driver dimensions
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2020-09-14 14:42:28 -07:00 |
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mrg
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55dd4d0c47
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Global bitcell array working
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2020-09-14 14:35:52 -07:00 |
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mrg
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deaaec1ede
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Fix width of write enable with spare columns
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2020-09-14 13:09:45 -07:00 |
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mrg
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c12720a93f
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Extend pin correct length in new array.
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2020-09-14 12:53:59 -07:00 |
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mrg
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e95ab66916
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Update to space according to the bitcell array.
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2020-09-14 12:05:45 -07:00 |
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mrg
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4482c63d6f
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Fix sense amp offset index error
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2020-09-11 17:12:29 -07:00 |
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mrg
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8909ad7165
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Update modules to use variable bit offsets.
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
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2020-09-11 15:36:22 -07:00 |
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mrg
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c58741c44f
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Updates to global array.
Standardize bitcell array main array offsets.
Duplicate replica interface pins in global interface pins.
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2020-09-10 16:44:54 -07:00 |
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mrg
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9c762634a5
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Change default options for replica_bitcell_array
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2020-09-10 15:11:48 -07:00 |
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mrg
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71d86f88b0
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Merge branch 'dev' into wlbuffer
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2020-09-10 13:05:14 -07:00 |
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mrg
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f2313d0c73
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Use default names for replica_column too
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2020-09-10 12:04:46 -07:00 |
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mrg
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3c0707e5d1
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Consistents of bl x port then br x port
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2020-09-09 13:38:13 -07:00 |
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mrg
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3062aba214
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Fix update to exclude bits with RBLs
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2020-09-09 13:03:05 -07:00 |
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mrg
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7bb21fb73f
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Updates to local and global arrays to make bitline and wordlines consistent.
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2020-09-09 11:54:46 -07:00 |
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mrg
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1269bf6e16
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Global bitcell working
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2020-09-04 13:06:58 -07:00 |
|
 Hunter Nichols
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8bcbf005bf
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Merge branch 'dev' into characterizer_bug_fixes
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2020-09-04 02:25:01 -07:00 |
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mrg
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1534295326
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Ground dummy lines in replica bitcell array
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2020-09-03 14:04:20 -07:00 |
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mrg
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f6f6242d68
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Ground dummy lines in replica bitcell array
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2020-09-03 10:45:28 -07:00 |
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jcirimel
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73443c8c95
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Merge branch 'dev' into s8_single_port
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2020-09-01 15:37:10 -07:00 |
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mrg
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4ec47d8ee1
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Refactor global and local to be a bitcell_base_array
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2020-09-01 11:59:01 -07:00 |
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mrg
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c1c631abe1
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Global bitcell array passes LVS/DRC
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2020-09-01 10:57:49 -07:00 |
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mrg
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7bdce3ca9a
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Don't make dummy bitlines pins for simplicity
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2020-09-01 09:55:23 -07:00 |
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Hunter Nichols
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73b2277daa
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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mrg
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c1c1535210
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Merge branch 'wlbuffer' into dev
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2020-08-27 15:44:29 -07:00 |
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mrg
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11a82b7283
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Fixed local bitcell array for single and dual port
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2020-08-27 14:03:05 -07:00 |
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mrg
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da827d923f
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Merge branch 'wlbuffer' into dev
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2020-08-26 10:00:34 -07:00 |
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mrg
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c321d85595
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Fix syntax error for dual port
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2020-08-26 09:54:41 -07:00 |
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mrg
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e92337ddaf
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Separate get_ and get_all for bitlines and wordlines
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2020-08-25 17:08:48 -07:00 |
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mrg
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652f160aca
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Merge branch 'wlbuffer' into dev
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2020-08-25 15:50:08 -07:00 |
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