 mrg
|
07d0f3af8e
|
Only copy end-cap pins to the bank level
|
2020-06-29 11:46:59 -07:00 |
|
|
mrg
|
1bc0775810
|
Only add pins to periphery
|
2020-06-29 10:03:24 -07:00 |
|
|
mrg
|
5285468380
|
All bitcells need a vdd/gnd pin
|
2020-06-28 15:09:47 -07:00 |
|
|
mrg
|
051c8d8697
|
Only add bitcells to dummy and replica rows and columns (the perimeter)
|
2020-06-28 14:47:54 -07:00 |
|
|
mrg
|
225fc69420
|
Use preferred routing direction
|
2020-06-28 14:29:12 -07:00 |
|
|
mrg
|
0c9f52e22f
|
Realign col decoder and control by 1/4 so metal can pass over
|
2020-06-28 07:15:06 -07:00 |
|
|
mrg
|
66ea559209
|
Use channel for dffs all at once
|
2020-06-27 08:23:12 -07:00 |
|
|
mrg
|
609aa98c8b
|
Move write mask pin to left of cell to avoid sense amp
|
2020-06-27 08:21:53 -07:00 |
|
|
mrg
|
2bd498c39c
|
Change precharge layer to m3
|
2020-06-27 08:21:30 -07:00 |
|
|
mrg
|
c07e20cbe4
|
Move mux select from li to m2 in sky130
|
2020-06-26 14:27:16 -07:00 |
|
|
mrg
|
f57eeb88eb
|
PEP8 cleanup, multiple vdd/gnd support
|
2020-06-26 11:47:55 -07:00 |
|
|
mrg
|
e23d41c1d4
|
PEP8 cleanup
|
2020-06-26 11:47:35 -07:00 |
|
|
mrg
|
66df659ad4
|
Col decoders are anything not bitcell pitch.
|
2020-06-25 14:25:48 -07:00 |
|
|
mrg
|
f84ee04fa9
|
Single bank passing.
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
|
2020-06-25 14:03:59 -07:00 |
|
|
mrg
|
93d65e84e1
|
Fix power pin layer problems in delay line
|
2020-06-24 10:26:49 -07:00 |
|
 Joey Kunzler
|
4e83e8c648
|
added contact to locali for wmask
|
2020-06-23 18:13:17 -07:00 |
|
|
mrg
|
cfa234a4d0
|
Extra space between decoders for well spacing
|
2020-06-23 15:39:42 -07:00 |
|
|
mrg
|
cd23b31ab4
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-06-22 12:55:45 -07:00 |
|
|
mrg
|
0926eab9f5
|
PEP8 formatting
|
2020-06-22 12:55:18 -07:00 |
|
|
Joey Kunzler
|
208c652653
|
added error for sky130 with invalid x mirroring (for lvs)
|
2020-06-19 13:59:33 -07:00 |
|
|
mrg
|
abb5ff7bae
|
Separate route conditions for s8
|
2020-06-15 10:30:27 -07:00 |
|
|
mrg
|
e331d6fae8
|
Permute bus order to avoid conflict in control_logic
|
2020-06-15 10:25:53 -07:00 |
|
|
mrg
|
79b3b9a8b0
|
Switch input/output layers for predecodes
|
2020-06-15 10:06:04 -07:00 |
|
|
mrg
|
02352c35d7
|
Fix hard coded layer in wmask
|
2020-06-14 17:10:32 -07:00 |
|
|
mrg
|
78be9f367a
|
Add brain-dead router pins to perimeter
|
2020-06-14 15:52:09 -07:00 |
|
|
mrg
|
33a32101c9
|
DRC and LVS fixes for pinv_dec
|
2020-06-12 15:23:51 -07:00 |
|
|
mrg
|
443b8fbe23
|
Change s8 to sky130
|
2020-06-12 14:23:26 -07:00 |
|
|
mrg
|
e9780ea599
|
Add non-preferred directions for channel routes
|
2020-06-11 15:03:36 -07:00 |
|
|
mrg
|
dff28a9997
|
Merge branch 'tech_migration' into dev
|
2020-06-10 17:09:05 -07:00 |
|
|
mrg
|
bfd1abc79f
|
Replica column pins start at 0 height.
|
2020-06-10 14:58:55 -07:00 |
|
|
mrg
|
157926960b
|
Flip freepdk45 flop, dff_buf route layer change
|
2020-06-09 13:48:16 -07:00 |
|
|
mrg
|
77fb7017c4
|
Merge branch 'tech_migration' into dev
|
2020-06-08 12:54:41 -07:00 |
|
|
mrg
|
9cc36c6d3a
|
Bus code converted to pins. Fix layers on control signal routes in bank.
|
2020-06-08 11:01:14 -07:00 |
|
 Aditi Sinha
|
300522a1a8
|
Change spare enable pins offset to lower right
|
2020-06-08 14:31:46 +00:00 |
|
|
Aditi Sinha
|
d5041afebc
|
Merge branch 'dev' into bisr
|
2020-06-07 16:27:25 +00:00 |
|
|
mrg
|
0837432d45
|
Wordline route layers and (optional) via.
|
2020-06-05 16:47:22 -07:00 |
|
|
mrg
|
5514996708
|
Auto-generate port dependent cell names.
|
2020-06-05 15:09:22 -07:00 |
|
|
mrg
|
00b51f5464
|
PEP8 format replica_bitcell_array
|
2020-06-05 13:49:32 -07:00 |
|
|
mrg
|
4fef632dce
|
Fix syntax error
|
2020-06-05 12:13:41 -07:00 |
|
|
mrg
|
a62b85a6b1
|
Update mirroring in port_data for bitcell mirrored arrays
|
2020-06-05 11:29:31 -07:00 |
|
|
mrg
|
e14deff3d1
|
Fixed offset in port_data
|
2020-06-04 16:03:39 -07:00 |
|
|
mrg
|
2fcecb7227
|
Variable zjog. 512 port address test. s8 port address working.
|
2020-06-04 16:01:32 -07:00 |
|
|
mrg
|
7aafa43897
|
Connect RBL to bottom of precharge cell
|
2020-06-04 10:22:52 -07:00 |
|
|
mrg
|
249b5355ba
|
Adjust rbl route
|
2020-06-03 17:08:04 -07:00 |
|
|
mrg
|
3927c62e32
|
Undo extra space due to nwell spacing
|
2020-06-03 16:39:33 -07:00 |
|
|
mrg
|
3b1fe26d25
|
Spacing between decoder and driver for s8
|
2020-06-03 14:33:30 -07:00 |
|
|
Joey Kunzler
|
6430aad857
|
Merge branch 'dev' into s8_update
|
2020-06-03 11:53:33 -07:00 |
|
|
Aditi Sinha
|
eb0c595dbe
|
SRAM layout and functional tests with spare cols
|
2020-06-03 12:31:30 +00:00 |
|
|
mrg
|
34209dac3d
|
A port option for correct mirroring in port_data.
|
2020-06-02 16:50:07 -07:00 |
|
|
Joey Kunzler
|
84021c9ccb
|
merge conflict 2 - port data
|
2020-06-02 16:32:08 -07:00 |
|