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OpenRAM
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4,968 Commits 5 Branches 63 Tags 79 MiB
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4968 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 0034798787 both rbl replica array working 2023-09-11 11:23:39 -07:00
vlsida-bot 1a8c27c549 Bump version: 1.2.34 -> 1.2.35 2023-09-09 22:09:16 +00:00
Eren Dogan b3e1a163d0 Fix derouting wires in the gridless router 2023-09-09 13:32:16 -07:00
Jesse Cirimelli-Low e553f3db41 fix sram.sp spare_wen 2023-09-07 12:24:39 -07:00
vlsida-bot 9c66473cc9 Bump version: 1.2.33 -> 1.2.34 2023-09-07 06:07:59 +00:00
Eren Dogan 995cc4f60f Fix typo 2023-09-06 21:38:19 -07:00
Eren Dogan 099869d4c9 Fix typos 2023-09-03 18:35:07 -07:00
Eren Dogan 3f2d61a0fa Prevent same file error when copying the config file (VLSIDA/PrivateRAM#108) 2023-09-03 18:21:31 -07:00
Jesse Cirimelli-Low eb82053ab8 copy router from dev 2023-09-03 13:16:18 -07:00
Jesse Cirimelli-Low 5605154cc2 merge dev 2023-09-02 12:27:38 -07:00
vlsida-bot 1a25fcf9a5 Bump version: 1.2.32 -> 1.2.33 2023-09-02 18:43:35 +00:00
Eren Dogan abb12bd785 Increase non-preferred direction cost in router 2023-09-02 08:00:58 -07:00
Eren Dogan 775922774a Use bbox trees to iterate over shapes in routing region efficiently 2023-09-01 20:37:07 -07:00
Jesse Cirimelli-Low 066d00f44b increase power ring crba width for drc 2023-09-01 02:02:41 -07:00
Eren Dogan d9004f6de6 Print more info for the routing processes 2023-08-31 19:03:31 -07:00
Eren Dogan 8a60684e51 Increase the routing region inflation to be safer 2023-08-31 18:26:45 -07:00
Eren Dogan a9e63efad7 Increase via cost in router 2023-08-31 18:26:04 -07:00
Jesse Cirimelli-Low c9a848550c Revert "merge dev" 
This reverts commit daec840888, reversing
changes made to 29e80e8f25.
 2023-08-30 22:40:35 -07:00
Jesse Cirimelli-Low daec840888 merge dev 2023-08-30 22:04:42 -07:00
Jesse Cirimelli-Low 29e80e8f25 bump sky130 sram library 2023-08-30 21:18:50 -07:00
Jesse Cirimelli-Low 0cba6a6050 single port sky130 crba passing lvs 2023-08-30 20:59:02 -07:00
vlsida-bot b281771753 Bump version: 1.2.31 -> 1.2.32 2023-08-30 16:52:07 +00:00
Eren Dogan 56bee27ee3 Don't write/read gds files unnecessarily for router 2023-08-29 21:45:52 -07:00
Jesse Cirimelli-Low 8f2e4c6914 power ring working 2023-08-28 22:15:05 -07:00
vlsida-bot b525ba60a0 Bump version: 1.2.30 -> 1.2.31 2023-08-28 21:12:21 +00:00
Jesse Cirimelli-Low 8794070ebc various refactor changes 2023-08-28 12:31:55 -07:00
Eren Dogan e12ab68362 Simplify closest edge calculation in signal escape router 2023-08-28 10:38:53 -07:00
Eren Dogan fa5de05be3 Merge branch 'dev' into gridless_router 2023-08-27 21:17:58 -07:00
Eren Dogan 53cc99f5c1 Perform signal escape routing in smaller regions 2023-08-27 21:16:34 -07:00
Eren Dogan 9df3c2ac59 Return the path in source-to-target order 2023-08-27 21:15:25 -07:00
Eren Dogan 141a4e3380 Don't scale the routing region if no path is found 2023-08-27 15:42:09 -07:00
Jesse Cirimelli-Low ba51149dce placement working for sp capped rba, need fix rowcap patterns 2023-08-26 18:54:07 -07:00
vlsida-bot 0ac2922573 Bump version: 1.2.29 -> 1.2.30 2023-08-26 22:17:23 +00:00
Jesse Cirimelli-Low ca5ca0c7a8 bump sram library commit to fix colenda gds 2023-08-26 15:29:08 -05:00
Jesse Cirimelli-Low 72a7b0342b work on capped rba 2023-08-25 16:39:32 -07:00
Jesse Cirimelli-Low 036cc54b99 rba done w/o wordline 2023-08-24 02:55:45 -07:00
Jesse Cirimelli-Low 64b0cd25d7 replica col passing 2023-08-22 01:16:35 -07:00
Jesse Cirimelli-Low a05ab6e908 route supplies + fix replica col dummy 2023-08-22 01:09:19 -07:00
Jesse Cirimelli-Low 450f8ab0c3 replica col generating, funny dummy cell placement 2023-08-22 00:45:57 -07:00
Jesse Cirimelli-Low 5cf50b333a bitcell array passing 2023-08-21 20:25:51 -07:00
Jesse Cirimelli-Low f890160601 add nwell routing in bca 2023-08-21 20:12:36 -07:00
Jesse Cirimelli-Low 5a6c78865d singleport bitcell array laying out 2023-08-21 19:24:06 -07:00
Jesse Cirimelli-Low 9ac894e2ef update bitcell array trimming 2023-08-15 11:30:16 -07:00
Sam Crow bb47452baf reapply commit c8a06a1 patch that was incorrectly reverted 2023-08-15 11:07:04 -07:00
Jesse Cirimelli-Low e4c15d33c4 Merge branch 'singleport_refactor' of github.com:VLSIDA/PrivateRAM into singleport_refactor 2023-08-14 18:53:22 -07:00
Sam Crow cd1b0f973d Revert pin/net spice object work 
This reverts commits 01116 6e3e9 2ced8 c67fd 2b9e7 bfabe 09aa3 5907c aa717 478c7 45b88 d0339 e15fe 7581d c8c43 146ef
 2023-08-14 18:44:51 -07:00
Jesse Cirimelli-Low 0391bf6593 add dummy mirroring for sky130 dp 2023-08-14 14:25:57 -07:00
Jesse Cirimelli-Low 30ee5a0a2e add dummy cell mirroring for sky130 2023-08-14 14:19:58 -07:00
Jesse Cirimelli-Low 74c12f944f mirror skywater dp 2023-08-14 13:59:31 -07:00
Jesse Cirimelli-Low fde1b056dc Merge branch 'dev' into singleport_refactor 2023-08-11 13:45:42 -07:00