Bugra Onal
be9fadf1bb
Base verilog template init
2022-07-21 15:45:50 -07:00
Bugra Onal
874d965edb
Template module done
2022-07-21 15:45:50 -07:00
Bugra Onal
99b517d55a
Bank select
2022-07-21 15:45:50 -07:00
Bugra Onal
54a012b574
Templatable verilog file
2022-07-21 15:45:50 -07:00
mrg
6707a93c3c
Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45.
2022-07-20 10:27:30 -07:00
mrg
5ad97aa636
Update README and setpaths with new PYTHONPATH
2022-07-20 10:27:10 -07:00
mrg
c406e2a9da
Make macros use same DOCKER_CMD.
2022-07-13 17:19:25 -07:00
mrg
ff7ceaf92d
Fix syntax error for module scope in row/col caps.
2022-07-13 17:19:09 -07:00
mrg
d92c7a634d
Use packages for imports.
...
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
2022-07-13 15:55:57 -07:00
mrg
58ea148d47
Add dlxtn latch for open reg file
2022-06-22 09:53:10 -07:00
mrg
f7738c60a3
Don't install SRAM macros.
2022-06-21 13:53:08 -07:00
mrg
ac86ad0e8a
Move pdk installation inside docker to use Magic from docker image.
2022-06-21 12:10:15 -07:00
Jesse Cirimelli-Low
374562f354
rbc substrate issues
2022-06-16 15:17:07 -07:00
mrg
c479915c02
Update colenda with new device sizes.
2022-06-16 11:23:13 -07:00
mrg
dc9ae6cd1a
Increase column width in netgen LVS scripts
2022-06-16 10:30:58 -07:00
Jesse Cirimelli-Low
98fe4c74a4
colend fixes in progress
2022-06-15 22:34:21 -07:00
mrg
69bb6826dc
Remove duplicate mount target
2022-06-14 12:08:56 -07:00
mrg
956fac2cec
Add patch.
2022-06-13 14:13:35 -07:00
mrg
c07f6d195f
Update docker to magic with patch for port first/next.
2022-06-13 14:13:20 -07:00
mrg
f0f2c26e8d
Add both sp and dp tiny test macro.
2022-06-13 14:13:05 -07:00
mrg
cf03454ecf
Don't add wdriver_sel_n pins which aren't used.
2022-06-10 09:18:40 -07:00
mrg
e744ffd6ea
Move mount to shared target in openram.mk
2022-06-09 06:44:23 -07:00
mrg
ef7120c5cd
Change pdk path in root directory mount command.
2022-06-09 06:38:33 -07:00
mrg
d30f05a1ae
Update power layer on li for sky130
2022-06-08 17:19:26 -07:00
mrg
9e3a28237f
Update port data test for sky130 single port
2022-06-08 17:18:53 -07:00
mrg
00ca2d45b6
Extract unique is option not command.
2022-06-08 15:06:06 -07:00
mrg
4814cf6eac
Merge branch 'sky130_fixes' into dev
2022-06-08 14:27:30 -07:00
mrg
280582d4d6
Add missing via in dff array
2022-06-08 14:24:17 -07:00
mrg
76bc4e1fc2
Only do one extract. Flatten transistors since bug fixed in magic.
2022-06-08 14:23:50 -07:00
mrg
910bcf9df3
Update magic to 8.3.310
2022-06-08 14:23:28 -07:00
mrg
ad6633ddca
Update versions of tools. Fix supply bug in predecode.
2022-06-08 13:50:25 -07:00
mrg
8fd062cea5
Resolve newest netgen version.
2022-06-07 12:10:47 -07:00
mrg
7b2f73d8b9
Update sky130_fd_bd_sram commit
2022-06-07 12:10:16 -07:00
Jesse Cirimelli-Low
d8ae19c0cd
update single port macros
2022-06-06 16:11:53 -07:00
Jesse Cirimelli-Low
4a400b225d
update netgen in dockerfile
2022-06-06 15:40:00 -07:00
Jesse Cirimelli-Low
fbe3032246
add case for single spare col spare_wen_dff i/o
2022-05-26 12:18:47 -07:00
mrg
1bab395946
Merge branch 'sky130_fixes' into dev
2022-05-24 09:12:37 -07:00
mrg
cb3d7b9d5d
Add spares for sky130 unit tests.
2022-05-23 17:27:26 -07:00
mrg
bbfccd1e00
Remove netlist bl/br swaps on flipped cells
2022-05-23 17:16:36 -07:00
mrg
b84b4dab43
Fail on pin mismatch too.
2022-05-23 16:28:28 -07:00
mrg
aed2ef4ecc
Add commit ids for PDK and open_pdks
2022-05-23 10:34:12 -07:00
mrg
8c85230033
Remove experimental power option.
2022-05-23 10:08:35 -07:00
mrg
51b0f125fb
Add offset to 0,0 that was inadvertantly removed for router debug.
2022-05-23 09:59:41 -07:00
Jesse Cirimelli-Low
825ada8293
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2022-05-19 21:51:13 -07:00
Jesse Cirimelli-Low
172d070880
fix bl routing in rba
2022-05-19 21:45:48 -07:00
mrg
25fa0a8de3
Fix missing cell syntax error.
2022-05-19 14:53:17 -07:00
mrg
18c04892d1
Set path for FREEPDK45 in ci.yml
2022-05-18 16:59:38 -07:00
mrg
735d66c9f1
Start dff array supplies on first rather than second bit.
2022-05-17 15:54:54 -07:00
mrg
3e02a0e7df
Update column decoder and dff array supplies
2022-05-17 15:49:50 -07:00
mrg
c8905c410a
Fix case where distance is zero length comparison
2022-05-17 15:49:06 -07:00
Bugra Onal
mrg
Jesse Cirimelli-Low