mirror of https://github.com/VLSIDA/OpenRAM.git
update single port macros
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4a400b225d
commit
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@ -13,6 +13,8 @@ write_size = 8 # Bits
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num_rw_ports = 1
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num_r_ports = 0
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num_w_ports = 0
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num_spare_rows = 1
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num_spare_cols = 1
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ports_human = '1rw'
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import os
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@ -13,6 +13,8 @@ write_size = 8 # Bits
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num_rw_ports = 1
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num_r_ports = 0
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num_w_ports = 0
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num_spare_rows = 1
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num_spare_cols = 1
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ports_human = '1rw'
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import os
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@ -14,6 +14,8 @@ write_size = 8 # Bits
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num_rw_ports = 1
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num_r_ports = 0
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num_w_ports = 0
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num_spare_rows = 1
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num_spare_cols = 1
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ports_human = '1rw'
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import os
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@ -0,0 +1,21 @@
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"""
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Single port, 1 kbytes SRAM, with byte write, useful for RISC-V processor main
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memory.
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"""
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word_size = 64 # Bits
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num_words = 512
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human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
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# Allow byte writes
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write_size = 8 # Bits
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# Single port
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num_rw_ports = 1
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num_r_ports = 0
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num_w_ports = 0
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num_spare_rows = 1
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num_spare_cols = 1
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ports_human = '1rw'
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import os
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exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())
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