Resolve newest netgen version.

macros/configs/sky130_sram_1kbyte_1rw_32x256_8.py

@@ -13,6 +13,8 @@ write_size = 8 # Bits
 num_rw_ports = 1
 num_r_ports = 0
 num_w_ports = 0
+num_spare_rows = 1
+num_spare_cols = 1
 ports_human = '1rw'
 
 import os

macros/configs/sky130_sram_2kbyte_1rw_32x512_8.py

@@ -13,6 +13,8 @@ write_size = 8 # Bits
 num_rw_ports = 1
 num_r_ports = 0
 num_w_ports = 0
+num_spare_rows = 1
+num_spare_cols = 1
 ports_human = '1rw'
 
 import os

macros/configs/sky130_sram_4kbyte_1rw_32x1024_8.py

@@ -14,6 +14,8 @@ write_size = 8 # Bits
 num_rw_ports = 1
 num_r_ports = 0
 num_w_ports = 0
+num_spare_rows = 1
+num_spare_cols = 1
 ports_human = '1rw'
 
 import os

macros/configs/sky130_sram_4kbyte_1rw_64x512_8.py

@@ -0,0 +1,21 @@
+"""
+Single port, 1 kbytes SRAM, with byte write, useful for RISC-V processor main
+memory.
+"""
+word_size = 64 # Bits
+num_words = 512
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Single port
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+num_spare_rows = 1
+num_spare_cols = 1
+ports_human = '1rw'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())