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add case for single spare col spare_wen_dff i/o

This commit is contained in:
Jesse Cirimelli-Low 2022-05-26 12:18:47 -07:00
parent 1bab395946
commit fbe3032246
1 changed files with 4 additions and 1 deletions
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5
compiler/sram/sram_base.py
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@ -688,7 +688,10 @@ class sram_base(design, verilog, lef):
inputs = []
outputs = []
for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}[{}]".format(port, bit))
if self.num_spare_cols == 1:
inputs.append("spare_wen{0}".format(port))
else:
inputs.append("spare_wen{0}[{1}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)