ThVerg
1123f733bd
sky130: use special_nfet_01v8 model for sub-0.42um nfets
...
The sky130 magic techfile splits nfet extraction on device width:
device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet ... w>=0.42
device msubcircuit sky130_fd_pr__special_nfet_01v8 scnfet ... w<0.42
ptx always emitted spice["nmos"], so every gate built from a
minimum-width device (drc["minwidth_tx"] = 0.36) was netlisted as
sky130_fd_pr__nfet_01v8 while magic extracted it as
sky130_fd_pr__special_nfet_01v8. netgen then reported a device class
mismatch in each such cell:
Circuit 1: sky130_fd_pr__special_nfet_01v8 (1) | Circuit 2: (no matching element)
Circuit 1: (no matching element) | Circuit 2: sky130_fd_pr__nfet_01v8 (1)
The signed-off macros shipped in sky130A/libs.ref/sky130_sram_macros use
special_nfet_01v8 at this geometry, so this restores the naming those
were built with.
ptx now asks the technology for a narrow-device model, keyed by width.
Technologies that declare no such model are unaffected, and there is no
equivalent split for pfets so only the nmos is declared.
After this change pinv and pinv_dec report "Netlists match uniquely"
where they previously mismatched. Verified with ngspice that
special_nfet_01v8 resolves through sky130.lib.spice, so characterization
is unaffected.
Co-Authored-By: Claude Opus 5 (1M context) <[email protected] https://claude.ai/code/session_01FcKSuKSchDEd7MqT8AffpN
2026-08-11 14:56:13 +02:00
Jesse Cirimelli-Low
ab33017fe2
Merge pull request #282 from ruhai-lin/stable
...
Attempt to fix LVS mismatch and SRAM creation with banks for sky130
2026-03-12 10:47:23 -07:00
rlin50
ec28bc6dfd
Fix sky130 1rw LVS mismatch by correcting col_cap pin order
2026-02-22 22:11:35 -08:00
Vikash Patel
b9bb6898af
Fix for Missing lef_rom_interconnect in tech.py
2025-10-17 14:40:03 +05:30
mrg
3f1f58065d
Add nand4 leakage to sky130 tech
2024-07-01 10:14:43 -07:00
mole99
85e242fa27
Add gf180mcu ROM example
2024-02-03 11:31:58 +01:00
Hadir Khan
bd9ebc3300
updated the spice file
2023-10-31 23:24:21 -07:00
hadirkhan10
561e0c228c
updated the cell name for layout and schematic
2023-10-31 23:24:21 -07:00
hadirkhan10
4b4153bdea
renamed the gds and sp file to reflect the cell name
2023-10-31 23:24:21 -07:00
hadirkhan10
98a4210b06
added the gds and spice of the bitcell
2023-10-31 23:24:21 -07:00
hadirkhan10
042bfcabea
added the custom cell definition
2023-10-31 23:24:21 -07:00
Hadir Khan
b65ebc6160
corrected the import statement and removed strap variant attribute which is no longer needed
2023-10-31 23:24:21 -07:00
SWalker
565e3f6814
flatten ptx in extraction and renumber test based on importance
2023-10-31 23:24:21 -07:00
SWalker
3271c5e73c
fixing drc on rom bank, mostly spacing tweaks
2023-10-31 23:24:21 -07:00
SWalker
75f7a5847f
fixing contact placement for gf180 in rom
2023-10-31 23:24:21 -07:00
SWalker
a544abebf7
fixed contact area issue
2023-10-31 23:24:21 -07:00
SWalker
20d0df2947
more boundary on the other side
2023-10-31 23:24:21 -07:00
Sage Walker
cb8567c66f
spacing tweaks for gf180 address control gate
2023-10-31 23:24:21 -07:00
SWalker
d940c0e03d
little more boundary
2023-10-31 23:24:21 -07:00
SWalker
23611f8fac
little more nwell
2023-10-31 23:24:21 -07:00
SWalker
e3b51360f3
extend nwell on nand
2023-10-31 23:24:21 -07:00
SWalker
ea703d124f
switched input pins on nand
2023-10-31 23:24:21 -07:00
SWalker
07fa78e00c
boundary shift for implant spacing
2023-10-31 23:24:21 -07:00
SWalker
dba75fc57c
boundary and alignment of nand
2023-10-31 23:24:21 -07:00
SWalker
9ac94d1744
even more nand
2023-10-31 23:24:21 -07:00
SWalker
0aa9c47f89
more nand
2023-10-31 23:24:21 -07:00
SWalker
8ac30f4ef5
proper gds for nand
2023-10-31 23:24:21 -07:00
SWalker
416140d04a
nand dup pin
2023-10-31 23:24:21 -07:00
SWalker
8c56478df3
more nand tweaks
2023-10-31 23:24:21 -07:00
SWalker
13459cb6dd
boundary box tweaks on dec nand
2023-10-31 23:24:21 -07:00
SWalker
88782b0a58
rotated nand2_dec
2023-10-31 23:24:21 -07:00
SWalker
4bb586c949
decoder nand custom cell
2023-10-31 23:24:21 -07:00
Sage Walker
d6cb15c82d
Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean.
2023-10-31 23:24:21 -07:00
Hadir Khan
698020301c
updates to add the port order overwrite attribute, ignore drc/lvs attribute and pwell as a non-routing layer
2023-10-31 23:24:21 -07:00
hadirkhan10
b9fd172e44
corrected the pin mapping
2023-10-31 23:24:21 -07:00
hadirkhan10
de7a248ff0
added the cell property definitions
2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low
a904874978
passing gf180 parameterized gate tests
2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low
d18a4f8c7c
additional tech commits
2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low
a18d62c430
rename gf180 to gf180mcu
2023-10-31 23:24:21 -07:00
mrg
06058e1b87
Initial files for gf180
2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low
788d7e5474
fix VPB/VNB pins not being found
2023-10-31 18:07:35 -07:00
Bugra Onal
d53353b5be
Merge branch 'dev' into char
2023-07-19 12:06:34 -07:00
Bugra Onal
eddc9af45b
Merge branch 'dev' into char
2023-07-10 13:55:50 -07:00
Sam Crow
539dfc979a
conform default behavior for sky130 custom modules to unit test
2023-06-07 17:31:12 -07:00
Bugra Onal
abd18ab832
Moved freepdk sense amp dout pin away from gnd pin
2023-05-23 15:08:06 -07:00
Bugra Onal
7ed99278bd
Sense amp fixes
2023-04-19 12:42:02 -07:00
Bugra Onal
dae275c508
Merge branch 'dev' into char
2023-04-12 12:00:31 -07:00
Bugra Onal
027b93ab83
Added buff to sense_amp in freepdk45
2023-04-12 11:49:55 -07:00
Bugra Onal
0ff1d1a23d
Added buff to sense_amp in scmos
2023-04-12 11:49:32 -07:00
Jacob Walker
ab955f0da8
removed data files
2023-03-30 11:30:50 -07:00
ThVerg
Jesse Cirimelli-Low
rlin50
Vikash Patel
mrg
mole99
Hadir Khan
SWalker
Sage Walker
Bugra Onal
Sam Crow
Bugra Onal