mirror of https://github.com/VLSIDA/OpenRAM.git
corrected the import statement and removed strap variant attribute which is no longer needed
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@ -6,7 +6,7 @@
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# All rights reserved.
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#
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import os
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import drc as d
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from openram import drc as d
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"""
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File containing the process technology parameters for Global Foundaries 180nm
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@ -59,7 +59,6 @@ cell_properties.nand2_dec.port_map = {'A': 'A',
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cell_properties.ptx.model_is_subckt = True
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cell_properties.use_strap = True
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cell_properties.strap_placement = 8 # this means strap cell gets placed after every 8 bitcells
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cell_properties.names["nand2_dec"] = ["gf180mcu_3v3__nand2_1_dec"]
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