luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #282 from ruhai-lin/stable

Browse Source 
Attempt to fix LVS mismatch and SRAM creation with banks for sky130
This commit is contained in:
Jesse Cirimelli-Low
2026-03-12 10:47:23 -07:00
committed by GitHub
parent c99b134deb 6d14626a75
commit ab33017fe2
5 changed files with 35 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
technology/sky130/custom/sky130_bitcell_base_array.py
+5 -4
View File
@@ -100,14 +100,15 @@ class sky130_bitcell_base_array(bitcell_base_array):
strap_pins = []
for port in self.all_ports:
strap_pins.extend([x for x in self.get_bitline_names(port) if "bl" in x and x.endswith("_{0}".format(col))])
strap_pins.extend(["vdd", "gnd"])
for port in self.all_ports:
strap_pins.extend([x for x in self.get_bitline_names(port) if "br" in x and x.endswith("_{0}".format(col))])
# col_cap_1port_bitcell port order:
# [bl, br, vdd, gnd, vpb, vnb, gate]
strap_pins.extend(["vdd", "gnd", "vdd", "gnd"])
if row == 0:
strap_pins.extend(["top_gate"])
strap_pins.append("top_gate")
else:
strap_pins.extend(["bot_gate"])
strap_pins.extend(["vdd", "gnd"])
strap_pins.append("bot_gate")
return strap_pins
def get_row_cap_pins(self, row, col):
technology/sky130/custom/sky130_col_cap_array.py
+6 -6
View File
@@ -75,12 +75,12 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
row_layout.append(self.colend1)
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
pins.append("fake_bl_{}".format(bitline))
pins.append("vdd")
pins.append("gnd")
pins.append("fake_br_{}".format(bitline))
pins.append("gate")
pins.append("vdd")
pins.append("gnd")
pins.append("vdd")
pins.append("gnd")
pins.append("gate")
bitline += 1
elif col % 4 == 1:
row_layout.append(self.colend2)
@@ -92,12 +92,12 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
row_layout.append(self.colend1)
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
pins.append("fake_bl_{}".format(bitline))
pins.append("vdd")
pins.append("gnd")
pins.append("fake_br_{}".format(bitline))
pins.append("gate")
pins.append("vdd")
pins.append("gnd")
pins.append("vdd")
pins.append("gnd")
pins.append("gate")
bitline += 1
elif col % 4 ==3:
row_layout.append(self.colend2)