luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

Add gf180mcu ROM example

Browse Source
This commit is contained in:
mole99
2024-02-03 11:31:58 +01:00
parent b6a6f12642
commit 85e242fa27
8 changed files with 48 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
technology/gf180mcu/tech/tech.py
+3
View File
@@ -97,6 +97,7 @@ m2_stack = ("m2", "via2", "m3")
m3_stack = ("m3", "via3", "m4")
m4_stack = ("m4", "via4", "m5")
lef_rom_interconnect = ["m1", "m2", "m3", "m4", "m5"]
layer_indices = {"poly": 0,
"active": 0,
@@ -182,6 +183,8 @@ layer_names["via2"] = "via2"
layer_names["m3"] = "metal3"
layer_names["via3"] = "via3"
layer_names["m4"] = "metal4"
layer_names["via4"] = "via4"
layer_names["m5"] = "metal5"
layer_names["text"] = "text"
layer_names["mem"] = "SramCore"
layer_names["boundary"]= "boundary"
technology/sky130/tech/tech.py
+2
View File
@@ -330,6 +330,8 @@ m2_stack = ("m2", "via2", "m3")
m3_stack = ("m3", "via3", "m4")
m4_stack = ("m4", "via4", "m5")
lef_rom_interconnect = ["m1", "m2", "m3", "m4"]
layer_indices = {"poly": 0,
"active": 0,
"nwell": 0,