mrg
b4cab6ec57
Change mult to 1 always.
2020-12-01 15:20:24 -08:00
Hunter Nichols
53e64fb696
Merge branch 'dev' into characterizer_bug_fixes
2020-11-20 11:16:41 -08:00
Hunter Nichols
9fd473ce70
Fixed issue with selection of column address when checking bitline names.
2020-11-20 01:11:08 -08:00
mrg
033111a5f3
Default to no hierarchical word lines.
2020-11-19 10:48:35 -08:00
Hunter Nichols
7a0f5e15db
Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later.
2020-11-17 15:05:07 -08:00
mrg
493c9125f1
Read different modules overrides for different num ports
2020-11-06 11:09:50 -08:00
mrg
ce7be7466f
Model as subckt for Magic too
2020-11-05 13:11:36 -08:00
mrg
da721a677d
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
mrg
ae0f4fe682
Fix spice model bin parameter error
2020-10-28 10:39:54 -07:00
mrg
acfec369d6
Add ptx cell properties
2020-10-28 09:54:15 -07:00
mrg
611a4155b9
Add initial custom layer properties.
2020-10-27 15:11:04 -07:00
mrg
dcd29214bc
Temp fix to use old device names during Calibre LVS.
2020-10-21 17:05:48 -07:00
mrg
af40f3077c
Change sky130 device cards to start with X
2020-10-15 13:56:10 -07:00
mrg
ca2ce8b070
Default bitcell opt1
2020-10-12 17:08:32 -07:00
jcirimel
4a1a7e637e
merge in dev
2020-10-07 11:54:07 -07:00
jcirimel
888646cdf9
merge in wlbuf and begin work on 32kb memory
2020-10-06 05:03:59 -07:00
mrg
4a58f09c1c
Use 4x16 decoder with dual port bitcell in tests.
2020-10-05 10:52:56 -07:00
mrg
c06b02e6fc
Rename single_level_column_mux to just column_mux
2020-10-05 08:56:51 -07:00
mrg
f8146e3f69
Add decoder4x16
2020-10-02 15:52:09 -07:00
mrg
1fc4040607
Add pand4 and pnand4
2020-10-02 14:54:12 -07:00
mrg
d65eb16513
Zjog the WL enable. Min driver is 1.
2020-09-28 12:24:55 -07:00
mrg
6f06bb9dd5
Create sized RBL WL driver in port_address
2020-09-28 11:30:21 -07:00
mrg
c7d32089f3
Create RBL wordline buffer with correct polarity.
2020-09-17 14:45:49 -07:00
Hunter Nichols
73b2277daa
Removed dead code related to older characterization scheme
2020-08-27 17:30:58 -07:00
jcirimel
854d51c721
merge dev
2020-08-19 14:25:41 -07:00
mrg
60224b105f
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2020-08-17 14:20:34 -07:00
jcirimel
e7c9914d77
decoder passing except for bus route
2020-08-13 16:20:39 -07:00
mrg
8dbaa66aa5
Merge branch 'super' into dev
2020-08-12 14:25:13 -07:00
mrg
7ac4574e4f
Use micron units for all simulation in sky130
2020-08-12 13:54:55 -07:00
mrg
5fc6438553
Fix pinv_dec super call
2020-08-12 13:22:28 -07:00
mrg
55814a8f74
Fix syntax errors in pgates for super edits
2020-08-12 11:15:32 -07:00
mrg
30976df48f
Change inheritance inits to use super
2020-08-06 11:33:26 -07:00
mrg
69cab42676
Add pbuf_dec gate
2020-07-27 13:59:55 -07:00
mrg
c7bc01c3a9
Clean up binning. Fix mults to 1 for certain gates.
2020-07-15 17:15:42 -07:00
mrg
e502ee02be
Place before computing height of col mux.
2020-07-13 15:51:46 -07:00
mrg
2b7d89d2c1
Fix netlist_only in sky130
2020-07-13 14:59:31 -07:00
mrg
e49236f8fc
Default drc and lvs errors is skipped.
2020-07-13 14:08:00 -07:00
mrg
c1fedda575
Modifications for min area metal.
...
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
2020-06-30 15:07:34 -07:00
mrg
c10a6a29c0
Simplify precharge pin layer
2020-06-27 08:22:16 -07:00
mrg
ee0a003298
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2020-06-25 08:57:37 -07:00
jcirimel
5941e01b51
add missing parens
2020-06-25 08:02:08 -07:00
jcirimel
59562f2b92
move accuracy_requirement from techfile to config
2020-06-25 06:44:07 -07:00
jcirimel
812cf11e95
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
2020-06-25 06:32:29 -07:00
jcirimel
57b6d49edb
fix pinv size bining
2020-06-25 06:32:07 -07:00
mrg
da900b89ba
Only expand implants in sky130
2020-06-24 13:48:30 -07:00
mrg
ba92467fec
Add no well enclosure for techs without wells
2020-06-24 12:07:47 -07:00
mrg
6c523a7556
use add_enclosure for npc contacts
2020-06-24 11:55:44 -07:00
mrg
e694622f28
use add_enclosure to extend implants
2020-06-24 11:54:59 -07:00
mrg
98ec9442c6
Add npc enclosure for pnand2, pnand3, pnor2
2020-06-24 10:00:00 -07:00
mrg
1340908330
Remove fudge factor for pin spacing
2020-06-24 09:24:26 -07:00
mrg
Hunter Nichols
jcirimel