 Matt Guthaus
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7eea63116f
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Control logic LVS clean
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2019-07-26 15:50:10 -07:00 |
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Matt Guthaus
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dce852d945
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Restructure control logic for improved drive and timing.
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2019-07-26 14:54:55 -07:00 |
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Matt Guthaus
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3327fa58c0
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Add some signal names to functional test comments
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2019-07-26 14:49:53 -07:00 |
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Matt Guthaus
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8ebc568e8b
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Minor cleanup. Skip more tests until analytical fixed.
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2019-07-26 08:33:06 -07:00 |
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Matt Guthaus
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20d9c30a64
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Use non-analytical models for now
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2019-07-25 14:55:42 -07:00 |
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Matt Guthaus
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88c399bc6c
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Skip prune test for now
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2019-07-25 14:49:11 -07:00 |
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Matt Guthaus
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d5419f99f6
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Skip model tests for now
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2019-07-25 14:46:33 -07:00 |
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Matt Guthaus
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c8c4d05bba
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Fix some regression fails.
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2019-07-25 14:18:08 -07:00 |
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Matt Guthaus
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0bb41b8a5d
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Fix duplicate paths for timing checks
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2019-07-25 13:25:58 -07:00 |
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Matt Guthaus
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80df996720
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Modify control logic for new RBL.
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2019-07-25 11:19:16 -07:00 |
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Matt Guthaus
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5452ed69e7
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Always have a precharge.
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2019-07-25 10:31:39 -07:00 |
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Matt Guthaus
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54b312eaf9
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Add return type
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2019-07-24 17:00:38 -07:00 |
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Matt Guthaus
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2f03c594c5
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Remove success initialization
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2019-07-24 16:59:19 -07:00 |
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Matt Guthaus
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cfc04064af
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Remove print.
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2019-07-24 16:57:57 -07:00 |
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Matt Guthaus
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fb60b51c72
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Add check bits. Clean up logic. Move read/write bit check to next cycle.
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2019-07-24 16:57:04 -07:00 |
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Matt Guthaus
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fe0db68965
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Refactor to share get_measurement_variant
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2019-07-24 11:29:29 -07:00 |
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Matt Guthaus
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9cb96bda7d
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Mostly formatting. Added write measurements.
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2019-07-24 10:57:33 -07:00 |
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Matt Guthaus
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3df8abd38c
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Clean up. Split class into own file.
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2019-07-24 08:15:10 -07:00 |
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Matt Guthaus
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07401fc6ea
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Make control bus routing offset consistent
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2019-07-23 09:39:28 -07:00 |
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Matt Guthaus
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864639d96e
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Remove old replica bitline.
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2019-07-18 15:19:40 -07:00 |
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Matt Guthaus
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a707c6fa50
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Convert psram tests to only 2 port.
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2019-07-18 14:49:54 -07:00 |
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 Hunter Nichols
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9696401f34
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Added graph exclusions to replica column to reduce s_en paths.
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2019-07-16 23:47:34 -07:00 |
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mrg
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e2602dd79b
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Add comments for pins. Fix noconn in dummy pbitcell.
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2019-07-16 17:30:31 -07:00 |
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mrg
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37fcf3bf37
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Move classes to individual file.
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2019-07-16 15:18:04 -07:00 |
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mrg
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8ca656959b
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Change direction of RBL bitline pins
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2019-07-16 15:09:46 -07:00 |
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mrg
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b546ecce2c
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Check 2 ports only for layout.
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2019-07-16 14:11:54 -07:00 |
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mrg
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12fa36317e
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Cleanup unit test. Fix s_en control bug for r-only.
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2019-07-16 13:51:31 -07:00 |
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mrg
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2f55911604
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Simplify column decoder placement.
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2019-07-16 11:55:25 -07:00 |
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mrg
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70ee026fcf
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Add cell names to psingle_bank test
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2019-07-16 11:54:57 -07:00 |
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mrg
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42ad0cd282
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Add pbitcell RW test
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2019-07-16 11:54:39 -07:00 |
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mrg
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f5804e1cbf
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Flatten bitcell array for LVS symmetries.
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2019-07-16 11:53:20 -07:00 |
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mrg
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bea07c2319
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SRAM with RBL integration in array.
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2019-07-16 09:04:58 -07:00 |
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mrg
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37c15937e2
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Add multiple control logic port types.
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2019-07-15 17:07:50 -07:00 |
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mrg
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e550d6ff10
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Port name maps between bank and replica array working.
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2019-07-15 11:29:29 -07:00 |
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mrg
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2271946eef
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Fix replica array pin names
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2019-07-12 14:39:56 -07:00 |
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mrg
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8815ddf7f1
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Remove unnecessary feasible period search.
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2019-07-12 11:55:42 -07:00 |
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mrg
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9092fa4ee6
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Remove multiport control logic test since it doesn't have a bitcell anymore.
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2019-07-12 11:18:47 -07:00 |
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mrg
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d72691f6c2
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Make mirror optional argument
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2019-07-12 11:14:47 -07:00 |
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mrg
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a189b325ed
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Merge remote-tracking branch 'origin/dev' into rbl_revamp
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2019-07-12 11:10:07 -07:00 |
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mrg
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80145c0a92
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Only enable pdb post-mortem when not purging temp for debug.
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2019-07-12 10:57:59 -07:00 |
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mrg
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17d144b5b5
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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mrg
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aa552f8e96
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Remove debug trace
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2019-07-12 10:17:33 -07:00 |
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mrg
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043018e8ba
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Functional tests working with new RBL.
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2019-07-12 08:42:36 -07:00 |
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mrg
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0b13225913
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Single banks working with new RBL
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2019-07-11 14:47:27 -07:00 |
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mrg
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b841fd7ce3
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Replica bitcell array with arbitrary RBLs working
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2019-07-10 15:56:51 -07:00 |
|
 Bin Wu
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c9c839ca46
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fix the delay measure bug in pex tests
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2019-07-10 04:39:40 -07:00 |
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Bin Wu
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e4070ddad8
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2
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2019-07-10 03:09:12 -07:00 |
|
 jsowash
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5258016c9f
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Changed location of port for din_reg.
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2019-07-06 12:27:24 -07:00 |
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jsowash
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6fe78fe04a
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Removed begin end for Verilog without wmask.
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2019-07-06 11:29:34 -07:00 |
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jsowash
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24bfaa3b76
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Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
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2019-07-05 15:55:03 -07:00 |
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