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Add comments for pins. Fix noconn in dummy pbitcell.

This commit is contained in:
mrg 2019-07-16 17:30:31 -07:00
parent 37fcf3bf37
commit e2602dd79b
2 changed files with 43 additions and 13 deletions
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10
compiler/base/hierarchy_spice.py
View File

@ -52,12 +52,13 @@ class spice():
def add_comment(self, comment):
""" Add a comment to the spice file """
try:
self.commments
except:
self.comments = []
else:
self.comments.append(comment)
self.comments.append(comment)
def add_pin(self, name, pin_type="INOUT"):
""" Adds a pin to the pins list. Default type is INOUT signal. """
@ -241,9 +242,12 @@ class spice():
sp.write("\n.SUBCKT {0} {1}\n".format(self.name,
" ".join(self.pins)))
for pin in self.pins:
sp.write("* {1:6}: {0} \n".format(pin,self.pin_type[pin]))
for line in self.comments:
sp.write("* {}\n".format(line))
# every instance must have a set of connections, even if it is empty.
if len(self.insts)!=len(self.conns):
debug.error("{0} : Not all instance pins ({1}) are connected ({2}).".format(self.name,

46
compiler/bitcells/pbitcell.py
View File

@ -30,12 +30,20 @@ class pbitcell(design.design):
self.dummy_bitcell = dummy_bitcell
design.design.__init__(self, name)
debug.info(2, "create a multi-port bitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
self.num_w_ports,
self.num_r_ports))
info_string = "{0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
self.num_w_ports,
self.num_r_ports)
debug.info(2, "create a multi-port bitcell with {}".format(info_string))
self.add_comment(info_string)
if self.dummy_bitcell:
self.add_comment("dummy bitcell")
if self.replica_bitcell:
self.add_comment("replica bitcell")
self.create_netlist()
# We must always create the bitcell layout because some transistor sizes in the other netlists depend on it
# We must always create the bitcell layout
# because some transistor sizes in the other netlists depend on it
self.create_layout()
self.add_boundary()
@ -377,14 +385,20 @@ class pbitcell(design.design):
# iterate over the number of read/write ports
for k in range(0,self.num_rw_ports):
bl_name = self.rw_bl_names[k]
br_name = self.rw_br_names[k]
if self.dummy_bitcell:
bl_name += "_noconn"
br_name += "_noconn"
# add read/write transistors
self.readwrite_nmos_left[k] = self.add_inst(name="readwrite_nmos_left{}".format(k),
mod=self.readwrite_nmos)
self.connect_inst([self.rw_bl_names[k], self.rw_wl_names[k], self.Q, "gnd"])
self.connect_inst([bl_name, self.rw_wl_names[k], self.Q, "gnd"])
self.readwrite_nmos_right[k] = self.add_inst(name="readwrite_nmos_right{}".format(k),
mod=self.readwrite_nmos)
self.connect_inst([self.Q_bar, self.rw_wl_names[k], self.rw_br_names[k], "gnd"])
self.connect_inst([self.Q_bar, self.rw_wl_names[k], br_name, "gnd"])
def place_readwrite_ports(self):
""" Places read/write ports in the bit cell """
@ -451,14 +465,20 @@ class pbitcell(design.design):
# iterate over the number of write ports
for k in range(0,self.num_w_ports):
bl_name = self.w_bl_names[k]
br_name = self.w_br_names[k]
if self.dummy_bitcell:
bl_name += "_noconn"
br_name += "_noconn"
# add write transistors
self.write_nmos_left[k] = self.add_inst(name="write_nmos_left{}".format(k),
mod=self.write_nmos)
self.connect_inst([self.w_bl_names[k], self.w_wl_names[k], self.Q, "gnd"])
self.connect_inst([bl_name, self.w_wl_names[k], self.Q, "gnd"])
self.write_nmos_right[k] = self.add_inst(name="write_nmos_right{}".format(k),
mod=self.write_nmos)
self.connect_inst([self.Q_bar, self.w_wl_names[k], self.w_br_names[k], "gnd"])
self.connect_inst([self.Q_bar, self.w_wl_names[k], br_name, "gnd"])
def place_write_ports(self):
""" Places write ports in the bit cell """
@ -533,6 +553,12 @@ class pbitcell(design.design):
# iterate over the number of read ports
for k in range(0,self.num_r_ports):
bl_name = self.r_bl_names[k]
br_name = self.r_br_names[k]
if self.dummy_bitcell:
bl_name += "_noconn"
br_name += "_noconn"
# add read-access transistors
self.read_access_nmos_left[k] = self.add_inst(name="read_access_nmos_left{}".format(k),
mod=self.read_nmos)
@ -545,11 +571,11 @@ class pbitcell(design.design):
# add read transistors
self.read_nmos_left[k] = self.add_inst(name="read_nmos_left{}".format(k),
mod=self.read_nmos)
self.connect_inst([self.r_bl_names[k], self.r_wl_names[k], "RA_to_R_left{}".format(k), "gnd"])
self.connect_inst([bl_name, self.r_wl_names[k], "RA_to_R_left{}".format(k), "gnd"])
self.read_nmos_right[k] = self.add_inst(name="read_nmos_right{}".format(k),
mod=self.read_nmos)
self.connect_inst(["RA_to_R_right{}".format(k), self.r_wl_names[k], self.r_br_names[k], "gnd"])
self.connect_inst(["RA_to_R_right{}".format(k), self.r_wl_names[k], br_name, "gnd"])
def place_read_ports(self):
""" Places the read ports in the bit cell """