luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,248 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

131 Commits

Author SHA1 Message Date
mrg 804814d18d Add bitlines to dummy modules 2020-10-16 13:43:56 -07:00
mrg 20be7caf98 Make conditional wl and bl for dummy rows/cols. 2020-10-15 13:56:37 -07:00
mrg 6a1f12b62d Refactored to utilize OOP 2020-10-13 11:07:31 -07:00
jcirimel 05667d784f move sky130 specific stuff to tech module lib 2020-10-13 04:48:10 -07:00
mrg 8d5db50062 Fix missing update for left RBL offset 2020-10-08 16:40:53 -07:00
mrg b0b15e8151 Fix indent bug that failed to create rbl wl pin labels. 2020-10-08 15:28:01 -07:00
mrg 01fe02bd90 Fixes to replica bitline array. 
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
 2020-10-08 14:53:44 -07:00
jcirimel 1e7ae06b7e fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end 2020-10-08 05:32:03 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 13e2a9f5f7 fix missed self.left_rbl refactor 2020-10-06 05:11:15 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg 449a4c2660 Exclude bitcells in other local areas not of interest 2020-09-29 12:15:42 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 70c90ca7fb Replica bitcell array bbox to include unused WL gnd pins. 2020-09-28 14:49:33 -07:00
jcirimel 3dd72cdeac progress with rba pin mismatch 2020-09-23 08:37:32 -07:00
jcirimel 17e6e5eb16 row end col done 2020-09-23 08:02:56 -07:00
jcirimel 5c263e0001 rep col done w/o power pins 2020-09-23 06:24:52 -07:00
mrg e7ad22ff69 Separate WL via from bitell array to avoid grounded WLs 2020-09-15 13:38:28 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg e95ab66916 Update to space according to the bitcell array. 2020-09-14 12:05:45 -07:00
mrg 8909ad7165 Update modules to use variable bit offsets. 
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
 2020-09-11 15:36:22 -07:00
mrg c58741c44f Updates to global array. 
Standardize bitcell array main array offsets.
Duplicate replica interface pins in global interface pins.
 2020-09-10 16:44:54 -07:00
mrg 9c762634a5 Change default options for replica_bitcell_array 2020-09-10 15:11:48 -07:00
mrg 71d86f88b0 Merge branch 'dev' into wlbuffer 2020-09-10 13:05:14 -07:00
mrg f2313d0c73 Use default names for replica_column too 2020-09-10 12:04:46 -07:00
mrg 3c0707e5d1 Consistents of bl x port then br x port 2020-09-09 13:38:13 -07:00
mrg 3062aba214 Fix update to exclude bits with RBLs 2020-09-09 13:03:05 -07:00
mrg 7bb21fb73f Updates to local and global arrays to make bitline and wordlines consistent. 2020-09-09 11:54:46 -07:00
mrg 1269bf6e16 Global bitcell working 2020-09-04 13:06:58 -07:00
Hunter Nichols 8bcbf005bf Merge branch 'dev' into characterizer_bug_fixes 2020-09-04 02:25:01 -07:00
mrg f6f6242d68 Ground dummy lines in replica bitcell array 2020-09-03 10:45:28 -07:00
mrg 4ec47d8ee1 Refactor global and local to be a bitcell_base_array 2020-09-01 11:59:01 -07:00
mrg 7bdce3ca9a Don't make dummy bitlines pins for simplicity 2020-09-01 09:55:23 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg 11a82b7283 Fixed local bitcell array for single and dual port 2020-08-27 14:03:05 -07:00
mrg c321d85595 Fix syntax error for dual port 2020-08-26 09:54:41 -07:00
mrg e92337ddaf Separate get_ and get_all for bitlines and wordlines 2020-08-25 17:08:48 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
mrg 8dee5520e0 Standardize array names independent of bitcell 2020-08-21 13:44:35 -07:00
mrg 593a98e29a Update local bitcell array for dual port 2020-08-19 11:35:55 -07:00
mrg e3e4bac922 Fix replica bitcell array for right only RBL 2020-08-18 15:47:52 -07:00
mrg e37a9234cc Update replica column call to new refactor 2020-08-18 09:14:50 -07:00
mrg 99e252d6d4 Update interface of RBL array 2020-08-17 17:19:07 -07:00
mrg 170e3feb7d Fix order of replica wordlines and bitlines 2020-08-14 14:14:49 -07:00
mrg 50525e70f4 Fix up to SRAM level with new replica bitcell array ports. 2020-08-13 14:29:10 -07:00
mrg a55909930f Replace replcia_bitcell_array with new one in bank 2020-08-12 09:49:14 -07:00
mrg 8e890c2014 Replica bitcell with all the fixings 2020-08-11 15:00:29 -07:00
mrg eef97ff215 Reabstracting bit and word line names. 2020-08-06 11:17:49 -07:00
mrg c260297366 Allow replica_bitcell_array without the replica columns for local wordlines. 2020-07-27 16:22:21 -07:00
mrg e1967dc548 Draft local and global arrays. Ensure rows before cols in usage. 2020-07-23 14:43:14 -07:00
mrg bec948dcc3 Fix error in when to add vias for array power 2020-06-29 15:28:55 -07:00
mrg 1bc0775810 Only add pins to periphery 2020-06-29 10:03:24 -07:00
mrg f84ee04fa9 Single bank passing. 
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
 2020-06-25 14:03:59 -07:00
mrg 00b51f5464 PEP8 format replica_bitcell_array 2020-06-05 13:49:32 -07:00
Joey Kunzler 218a553ac5 fix for replica column mirroring over y 2020-05-28 20:31:21 -07:00
Joey Kunzler 7505fa5aef update for end caps 2020-05-27 20:03:11 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
Bastian Koppelmann f6302caeac replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names 
this allows us to override the bl/br/wl names of each bitcell.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:37:47 +01:00
jcirimel b212b3e85a s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00
mrg 0880c393fd Fix base bitcell syntax error. Remove some unused imports. 2020-01-30 01:58:30 +00:00
Bastian Koppelmann dd1afe0313 Bitcell arrays: Allow mirroring on the y axis 
this allows for bitcells that need to be mirrored on the y axis, like
thin cells. However, the portdata elements also need to be mirrored on
the y axis. Otherwise the router will fail horribly when connecting
bitlines.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:51:21 +01:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Matt Guthaus 8d6a4c74e7 Merge branch 'dev' into control_fix 2019-08-10 13:07:30 -07:00
Hunter Nichols 3c44ce2df6 Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer. 2019-08-08 02:33:51 -07:00
Matt Guthaus d36f14b408 New control logic, netlist only working 2019-08-07 17:14:33 -07:00
Hunter Nichols 2efc0a3983 Merge branch 'dev' into analytical_cleanup 2019-08-06 14:51:30 -07:00
Hunter Nichols 24b1fa38a0 Added graph fixes to handmade multiport cells. 2019-07-30 20:31:32 -07:00
Hunter Nichols dc46d07ca3 Removed unused code for input loads 2019-07-26 14:20:47 -07:00
Matt Guthaus c8c4d05bba Fix some regression fails. 2019-07-25 14:18:08 -07:00
Hunter Nichols 9696401f34 Added graph exclusions to replica column to reduce s_en paths. 2019-07-16 23:47:34 -07:00
mrg 8ca656959b Change direction of RBL bitline pins 2019-07-16 15:09:46 -07:00
mrg e550d6ff10 Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
mrg 2271946eef Fix replica array pin names 2019-07-12 14:39:56 -07:00
mrg 043018e8ba Functional tests working with new RBL. 2019-07-12 08:42:36 -07:00
mrg 0b13225913 Single banks working with new RBL 2019-07-11 14:47:27 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
mrg 9dab0be737 Single bank working with replica array. 2019-07-05 13:44:29 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00