mirror of https://github.com/VLSIDA/OpenRAM.git
Removed unused code for input loads
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@ -197,15 +197,6 @@ class bitcell_array(design.design):
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def output_load(self, bl_pos=0):
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bl_wire = self.gen_bl_wire()
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return bl_wire.wire_c # sense amp only need to charge small portion of the bl
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# set as one segment for now
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def input_load(self):
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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def get_wordline_cin(self):
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"""Get the relative input capacitance from the wordline connections in all the bitcell"""
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#A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
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@ -330,15 +330,6 @@ class replica_bitcell_array(design.design):
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def gen_wl_wire(self):
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if OPTS.netlist_only:
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width = 0
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else:
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width = self.width
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wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_metal1"))
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wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
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return wl_wire
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def gen_bl_wire(self):
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if OPTS.netlist_only:
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height = 0
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@ -349,15 +340,6 @@ class replica_bitcell_array(design.design):
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def output_load(self, bl_pos=0):
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bl_wire = self.gen_bl_wire()
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return bl_wire.wire_c # sense amp only need to charge small portion of the bl
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# set as one segment for now
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def input_load(self):
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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def get_wordline_cin(self):
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"""Get the relative input capacitance from the wordline connections in all the bitcell"""
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#A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
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