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OpenRAM
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188 Commits

Author SHA1 Message Date
Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass. 2018-10-30 22:19:26 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Matt Guthaus ab7a83b7a5 Remove old setup.tcl and edit one in tech dir 2018-10-20 15:20:15 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Matt Guthaus 823cb04b80 Fix metal4 rules in FreePDK45. Multiport still needs updating. 2018-10-11 09:56:15 -07:00
Matt Guthaus 1ed74cd571 Add minarea_metal4 in freepdk45 2018-10-10 15:33:16 -07:00
Matt Guthaus c0ffa9cc7b Clean up magic config file copying. Add warning for missing files. 2018-10-05 08:36:12 -07:00
Matt Guthaus b3fa6b9d52 Make setup.tcl file a technology file 2018-10-05 08:30:25 -07:00
Matt Guthaus 8d2804b9cb Supply router working except: 
Off grid pins. Some pins do now span enough of the routing track and must be patched.
  Route track width. Instead of minimum width route, it should be the track width.
 2018-09-18 12:57:39 -07:00
Matt Guthaus 60cceab50a Merge branch 'dev' into supply_routing 2018-09-17 11:34:31 -07:00
Matt Guthaus f4389bdd8f Add extra track spacings in some routes. 2018-09-13 14:12:24 -07:00
Matt Guthaus c9806feb01 Add convert script for mag to gds 2018-09-13 12:55:10 -07:00
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
 2018-09-13 12:53:35 -07:00
Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 2018-09-13 11:40:24 -07:00
Matt Guthaus 6ab4f5363a Initial scn4me_subm cells and rules. 2018-09-13 11:03:35 -07:00
Matt Guthaus f8fc7c12b3 Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
Matt Guthaus 30a77f8527 Convert scn3me_subm tech to lambda rules 2018-09-13 11:01:30 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Matt Guthaus ee05865919 Change SCMOS comment drawing to stipple for easier visibility 2018-09-05 13:43:45 -07:00
Matt Guthaus 93b24d8c85 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-09-05 11:05:41 -07:00
Matt Guthaus 2a27fbc98e Fix temp directory preservation option. 
Make labels in freepdk45 replica bitcell lower case.
 2018-09-05 10:02:12 -07:00
Matt Guthaus 73e2bd2653 Removed solid display format for comments to allow grid/blockage visibility. 2018-09-04 16:43:59 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus d721fae5b0 Change labels in replica cell for freepdk45 too 2018-09-04 14:33:14 -07:00
Matt Guthaus 763f1e8dee Finish renaming replica bitcell and bitline pin names. 2018-09-04 14:03:15 -07:00
Matt Guthaus 4fc9278b73 Convert bounding box layer for SCMOS to bb, gds layer 63. 2018-09-04 13:05:21 -07:00
Matt Guthaus c3bd54696f Merge branch 'dev' into multiport 2018-08-31 12:56:25 -07:00
Matt Guthaus 3ab0b569cb Use a .magicrc in the technology directory to read magic tech files 2018-08-30 14:20:41 -07:00
Matt Guthaus e36452622c Preserve same order of design rules in each tech file 2018-08-29 16:12:06 -07:00
Michael Timothy Grimes 1f53a82d56 Fixed name for poly_to_polycontact rule. Previously said poly_to_contactpoly in error. 2018-08-29 15:04:17 -07:00
Michael Timothy Grimes 0182309f92 Editting comment on rule 5.5.b in scmos tech file. Adding complimentary rule to freepdk45 tech file. 2018-08-29 14:51:50 -07:00
Matt Guthaus 6e332e581a Updated to include local magic rules 2018-08-15 09:46:23 -07:00
Matt Guthaus 49bee6a96e Remove OEB signal since we split DIN/DOUT ports 2018-08-13 14:09:49 -07:00
Matt Guthaus 368ab718d6 Change internal nets of 6T cell and write driver to have useful names for debugging. 2018-07-26 11:26:47 -07:00
Michael Timothy Grimes 8f131ddb2f commiting changes from most recent pull from dev 2018-05-22 17:30:51 -07:00
Michael Timothy Grimes d8cb3653e0 changing case of pins in handmade cell_6t for freepdk45 2018-05-22 14:19:26 -07:00
Michael Timothy Grimes 766042fe69 changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit 2018-05-22 14:16:51 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus 85b7b73903 Flip sense amp y axis 2018-04-23 10:19:26 -07:00
Matt Guthaus 269d553857 Move sense amp to tri gate routing to M3... not ideal. 2018-04-23 09:14:18 -07:00
Matt Guthaus e1f4c933e1 Flip sense amp and increase pin size 2018-04-20 17:04:26 -07:00
Matt Guthaus 248decd004 Hand edit sense amp to have full pins rather than split from magic gds write. 2018-04-20 15:46:39 -07:00
Matt Guthaus c75eafe085 Fix some errors 2018-04-18 09:37:33 -07:00
Matt Guthaus 63a8f7c653 Remove m2 from write driver 2018-04-16 16:15:35 -07:00
Matt Guthaus e2f93a0a99 Fix via overlap DRC error 2018-04-11 15:48:40 -07:00
Matt Guthaus ef99d13f1b Fix via overlap DRC error 2018-04-11 15:46:44 -07:00
Matt Guthaus 6640d3491d Tri gate and array supply to M2 and M3 2018-04-11 15:11:47 -07:00
Matt Guthaus 06c132b695 Fix drc overlap error 2018-04-11 15:00:56 -07:00
Matt Guthaus 21bc5b7d05 Fix drc overlap error 2018-04-11 14:59:04 -07:00
Matt Guthaus 14ff20fc9e Fix drc overlap error 2018-04-11 14:56:59 -07:00
Matt Guthaus d1862eda90 Fix drc overlap error 2018-04-11 14:55:04 -07:00
Matt Guthaus 46c18f53ba Add M2 vias in ms_flop 2018-04-11 14:10:57 -07:00
Matt Guthaus 0e6720be66 Fix write driver gnd pin layer text 2018-04-11 09:34:13 -07:00
Matt Guthaus 4f8ab78ee2 Change write driver supply pins to M2 2018-04-11 09:29:54 -07:00
Matt Guthaus 80829aa0af Sense amp vdd/gnd to M2 2018-04-06 17:15:36 -07:00
Matt Guthaus a6c2e77bcf Move precharge and column mux cells to pgate directory. 
Move gnd to M3 in column mux.
Create column mux cell unit test.
 2018-04-06 17:15:14 -07:00
Matt Guthaus a35fc1f339 Add contact to cell6t and replica. 2018-04-04 13:18:12 -07:00
Matt Guthaus a0bf5345f8 Mostly working for 1 bank. 2018-03-23 08:14:26 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus c020d74f26 Add dff_buf and dff_array modules. 2018-03-23 08:11:51 -07:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
Matt Guthaus fc441fe568 Add LICENSE and README from NCSU CDK 2018-03-02 10:42:23 -08:00
Matt Guthaus 7293eb33bc Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-03-02 10:30:16 -08:00
Matt Guthaus ae2dbb4cd5 Add display techfiles from NCSU PDKs. 2018-03-02 10:30:03 -08:00
Hunter Nichols d0dcd9f34b Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
Hunter Nichols 9317eb7e8b Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into analytical_power 2018-03-01 20:52:40 -08:00
Matt Guthaus 9a6081de0e Remove KP from SCMOS models to get rid of ngspice error. 2018-03-01 11:10:04 -08:00
Hunter Nichols e6d6680da1 Fixed conflict in delay.py 2018-02-27 13:02:22 -08:00
Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins. 2018-02-27 08:59:46 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high. 2018-02-23 12:21:32 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
Matt Guthaus b31f3c18af Change BSIM3 models to version 3.3.0. Add comment about multithreading selection. 2018-02-21 17:50:12 -08:00
mguthaus 5e8dff1e90 Fix unit tests with newest RBL delays. Fix tech problem with new spice models. 2018-02-16 13:54:05 -08:00
mguthaus 1297cb4e40 Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell. 2018-02-16 10:40:05 -08:00
Matt Guthaus bab9ae8201 Fix off-grid pin and overlap problems for pins in freepdk dff cell. 2018-02-15 17:54:26 -08:00
Matt Guthaus e66a37c916 Put DFF pins on 2.5nm grid in 45nm. 2018-02-15 11:08:57 -08:00
Matt Guthaus 2d3acb03a1 Add bbox for dff in freepdk45 2018-02-14 17:04:31 -08:00
Matt Guthaus d89e49aecc Add metal2 pins to freepdk45 dff. 2018-02-14 16:58:41 -08:00
Matt Guthaus 9559421ca8 Connect dff array clk in rows and columns. 2018-02-14 16:46:26 -08:00
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
Matt Guthaus ccc8ed2b48 Add slow and fast SCMOS spice models. 2018-02-12 17:16:40 -08:00
mguthaus 6bf4190dde Fix missing tech name in path to spice models. Rename models to p,n. 2018-02-12 10:24:15 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus f4a99be9d8 Add poly_to_field_poly rule in SCMOS 2018-02-08 16:08:20 -08:00
Matt Guthaus ed194ad47b Remove spice dir env variable for freepdk. 2018-02-07 10:05:21 -08:00
Matt Guthaus 4505c0f74e Improve error to setup model dir path. Use it to override FreePDK45 too. 2018-02-05 15:12:12 -08:00
Matt Guthaus 6f8744712d Add extra pwc to 6T SCMOS cell. 2018-02-05 14:44:15 -08:00
Matt Guthaus fb90b8f5fe Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
Matt Guthaus 64546ad3dd Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00