mirror of https://github.com/VLSIDA/OpenRAM.git
Add poly_to_field_poly rule in SCMOS
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@ -76,7 +76,7 @@ drc["pwell_to_nwell"] = 0
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drc["minwidth_well"] = 3.6
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# 3.1 Minimum width
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drc["minwidth_poly"] = 0.6
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# 3.2/3.2.a Minimum spacing over field/active
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# 3.2 Minimum spacing over active
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drc["poly_to_poly"] = 0.9
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# 3.3 Minimum gate extension of active
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drc["poly_extend_active"] = 0.6
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@ -84,6 +84,8 @@ drc["poly_extend_active"] = 0.6
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drc["poly_to_polycontact"] = 1.2
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# ??
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drc["active_enclosure_gate"] = 0.0
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# 3.2.a Minimum spacing over field poly
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drc["poly_to_field_poly"] = 0.9
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# 3.5 Minimum field poly to active
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drc["poly_to_active"] = 0.3
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# Not a rule
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