mirror of https://github.com/VLSIDA/OpenRAM.git
Convert scn3me_subm tech to lambda rules
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@ -50,17 +50,18 @@ layer["blockage"] = 83
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###################################################
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##DRC/LVS Rules Setup
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###################################################
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_lambda_ = 0.3
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#technology parameter
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parameter={}
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parameter["min_tx_size"] = 1.2
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parameter["min_tx_size"] = 4*_lambda_
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parameter["beta"] = 2
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drclvs_home=os.environ.get("DRCLVS_HOME")
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drc={}
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#grid size is 1/2 a lambda
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drc["grid"]=0.15
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drc["grid"]=0.5*_lambda_
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#DRC/LVS test set_up
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drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul"
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drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
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@ -68,52 +69,52 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
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# minwidth_tx with contact (no dog bone transistors)
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drc["minwidth_tx"] = 1.2
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drc["minlength_channel"] = 0.6
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drc["minwidth_tx"] = 4*_lambda_
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drc["minlength_channel"] = 2*_lambda_
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# 1.3 Minimum spacing between wells of same type (if both are drawn)
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drc["well_to_well"] = 1.8
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drc["well_to_well"] = 6*_lambda_
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# 1.4 Minimum spacing between wells of different type (if both are drawn)
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drc["pwell_to_nwell"] = 0
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# 1.1 Minimum width
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drc["minwidth_well"] = 3.6
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drc["minwidth_well"] = 12*_lambda_
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# 3.1 Minimum width
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drc["minwidth_poly"] = 0.6
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drc["minwidth_poly"] = 2*_lambda_
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# 3.2 Minimum spacing over active
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drc["poly_to_poly"] = 0.9
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drc["poly_to_poly"] = 3*_lambda_
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# 3.3 Minimum gate extension of active
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drc["poly_extend_active"] = 0.6
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drc["poly_extend_active"] = 2*_lambda_
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# 5.5.b Minimum spacing between poly contact and other poly (alternative rules)
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drc["poly_to_polycontact"] = 1.2
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drc["poly_to_polycontact"] = 4*_lambda_
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# ??
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drc["active_enclosure_gate"] = 0.0
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# 3.5 Minimum field poly to active
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drc["poly_to_active"] = 0.3
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drc["poly_to_active"] = _lambda_
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# 3.2.a Minimum spacing over field poly
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drc["poly_to_field_poly"] = 0.9
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drc["poly_to_field_poly"] = 3*_lambda_
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# Not a rule
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drc["minarea_poly"] = 0.0
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# ??
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drc["active_to_body_active"] = 1.2 # Fix me
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drc["active_to_body_active"] = 4*_lambda_ # Fix me
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# 2.1 Minimum width
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drc["minwidth_active"] = 0.9
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drc["minwidth_active"] = 3*_lambda_
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# 2.2 Minimum spacing
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drc["active_to_active"] = 0.9
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drc["active_to_active"] = 3*_lambda_
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# 2.3 Source/drain active to well edge
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drc["well_enclosure_active"] = 1.8
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drc["well_enclosure_active"] = 6*_lambda_
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# Reserved for asymmetric enclosures
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drc["well_extend_active"] = 1.8
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drc["well_extend_active"] = 6*_lambda_
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# Not a rule
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drc["minarea_active"] = 0.0
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# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width
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drc["implant_to_channel"] = 0.9
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drc["implant_to_channel"] = 3*_lambda_
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# 4.2 Minimum select overlap of active
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drc["implant_enclosure_active"] = 0.6
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drc["implant_enclosure_active"] = 2*_lambda_
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# 4.3 Minimum select overlap of contact
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drc["implant_enclosure_contact"] = 0.3
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drc["implant_enclosure_contact"] = _lambda_
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# Not a rule
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drc["implant_to_contact"] = 0
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# Not a rule
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@ -122,70 +123,70 @@ drc["implant_to_implant"] = 0
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drc["minwidth_implant"] = 0
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# 6.1 Exact contact size
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drc["minwidth_contact"] = 0.6
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drc["minwidth_contact"] = 2*_lambda_
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# 5.3 Minimum contact spacing
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drc["contact_to_contact"] = 0.9
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drc["contact_to_contact"] = 3*_lambda_
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# 6.2.b Minimum active overlap
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drc["active_enclosure_contact"] = 0.3
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drc["active_enclosure_contact"] = _lambda_
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# Reserved for asymmetric enclosure
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drc["active_extend_contact"] = 0.3
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drc["active_extend_contact"] = _lambda_
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# 5.2.b Minimum poly overlap
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drc["poly_enclosure_contact"] = 0.3
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drc["poly_enclosure_contact"] = _lambda_
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# Reserved for asymmetric enclosures
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drc["poly_extend_contact"] = 0.3
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drc["poly_extend_contact"] = _lambda_
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# Reserved for other technologies
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drc["contact_to_gate"] = 0.6
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drc["contact_to_gate"] = 2*_lambda_
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# 5.4 Minimum spacing to gate of transistor
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drc["contact_to_poly"] = 0.6
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drc["contact_to_poly"] = 2*_lambda_
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# 7.1 Minimum width
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drc["minwidth_metal1"] = 0.9
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drc["minwidth_metal1"] = 3*_lambda_
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# 7.2 Minimum spacing
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drc["metal1_to_metal1"] = 0.9
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drc["metal1_to_metal1"] = 3*_lambda_
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# 7.3 Minimum overlap of any contact
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drc["metal1_enclosure_contact"] = 0.3
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drc["metal1_enclosure_contact"] = _lambda_
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# Reserved for asymmetric enclosure
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drc["metal1_extend_contact"] = 0.3
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drc["metal1_extend_contact"] = _lambda_
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# 8.3 Minimum overlap by metal1
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drc["metal1_enclosure_via1"] = 0.3
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drc["metal1_enclosure_via1"] = _lambda_
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# Reserve for asymmetric enclosures
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drc["metal1_extend_via1"] = 0.3
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drc["metal1_extend_via1"] = _lambda_
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# Not a rule
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drc["minarea_metal1"] = 0
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# 8.1 Exact size
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drc["minwidth_via1"] = 0.6
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drc["minwidth_via1"] = 2*_lambda_
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# 8.2 Minimum via1 spacing
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drc["via1_to_via1"] = 0.6
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drc["via1_to_via1"] = 2*_lambda_
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# 9.1 Minimum width
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drc["minwidth_metal2"] = 0.9
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drc["minwidth_metal2"] = 3*_lambda_
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# 9.2 Minimum spacing
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drc["metal2_to_metal2"] = 0.9
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drc["metal2_to_metal2"] = 3*_lambda_
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# 9.3 Minimum overlap of via1
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drc["metal2_extend_via1"] = 0.3
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drc["metal2_extend_via1"] = _lambda_
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via1"] = 0.3
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drc["metal2_enclosure_via1"] = _lambda_
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# 14.3 Minimum overlap by metal2
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drc["metal2_extend_via2"] = 0.3
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drc["metal2_extend_via2"] = _lambda_
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via2"] = 0.3
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drc["metal2_enclosure_via2"] = _lambda_
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# Not a rule
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drc["minarea_metal2"] = 0
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# 14.2 Exact size
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drc["minwidth_via2"] = 0.6
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drc["minwidth_via2"] = 2*_lambda_
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# 14.2 Minimum spacing
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drc["via2_to_via2"] = 0.9
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drc["via2_to_via2"] = 3*_lambda_
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# 15.1 Minimum width
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drc["minwidth_metal3"] = 1.5
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drc["minwidth_metal3"] = 5*_lambda_
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# 15.2 Minimum spacing to metal3
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drc["metal3_to_metal3"] = 0.9
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drc["metal3_to_metal3"] = 3*_lambda_
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# 15.3 Minimum overlap of via 2
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drc["metal3_extend_via2"] = 0.6
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drc["metal3_extend_via2"] = 2*_lambda_
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# Reserved for asymmetric enclosures
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drc["metal3_enclosure_via2"] = 0.6
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drc["metal3_enclosure_via2"] = 2*_lambda_
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# Not a rule
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drc["minarea_metal3"] = 0
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