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OpenRAM
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2,727 Commits 4 Branches 63 Tags 78 MiB
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2727 Commits

Author SHA1 Message Date
mrg 64d61f4d56 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 12:16:41 -07:00
mrg f23d2e36a7 Don't obstruct control logic signals with dffs when no column mux. 2020-07-29 10:31:18 -07:00
mrg 8a2fa90cd5 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 10:11:26 -07:00
Hunter Nichols b4dafac489 Fixed issue with sen measurement not being added 2020-07-27 23:55:03 -07:00
Hunter Nichols 9ea3616260 Changed multiport characterization warning to better fit 2020-07-27 15:47:02 -07:00
Hunter Nichols c65178f86c Fixed issue with sen delay measure getting mixed with voltage checks 2020-07-27 15:43:50 -07:00
mrg 317662d4aa Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-23 14:17:52 -07:00
mrg b7c43ae674 Fix 1w/1r example 2020-07-23 14:17:13 -07:00
mrg 58846a4a25 Limit wordline driver size. Place row addr dff near predecoders. 2020-07-20 17:57:38 -07:00
mrg 0ed81aa923 Removed extraneous shift from added mirroring 2020-07-20 14:11:52 -07:00
mrg 82bbacdfb5 Add data bus gap to dynamically computed channel width 2020-07-20 13:43:57 -07:00
mrg a36e89e103 Replace data flops depending on channel width 2020-07-20 13:26:05 -07:00
mrg 2ccf3aea3b Set channel route height and width (of routes, not pins) 2020-07-20 13:25:47 -07:00
mrg f87b427f76 Add parent to channel route for dumpign debug gds. 2020-07-20 12:03:25 -07:00
mrg f35848e4f8 Route col flops separately. Flip port 1 col flop for easier routing. 2020-07-20 12:02:59 -07:00
mrg 7385decbff Add channel route cyclic VCG debugging. 2020-07-20 12:02:30 -07:00
mrg 80070dff41 Move write_driver din left to avoid control signal in spare columns. 2020-07-16 14:47:14 -07:00
mrg 9d5d632d1a Pins may be below the channel. 2020-07-16 14:23:48 -07:00
mrg ba3d32fa0c Starting to implement minimizing channel router (not done) 2020-07-16 13:21:44 -07:00
mrg 919e6a5027 Merge remote-tracking branch 'private/dev' into dev 2020-07-15 19:47:44 -07:00
mrg c7bc01c3a9 Clean up binning. Fix mults to 1 for certain gates. 2020-07-15 17:15:42 -07:00
mrg bb8157b3b7 Exit on DRC not run, check for LVSDRC before running in sram_base. 2020-07-14 08:38:49 -07:00
mrg ed9d32c7bc OpenRAM 1.1.6 2020-07-13 16:26:25 -07:00
mrg b4f5dc4c6e OpenRAM 1.1.6 2020-07-13 16:25:55 -07:00
mrg e502ee02be Place before computing height of col mux. 2020-07-13 15:51:46 -07:00
mrg 2b7d89d2c1 Fix netlist_only in sky130 2020-07-13 14:59:31 -07:00
mrg e49236f8fc Default drc and lvs errors is skipped. 2020-07-13 14:08:00 -07:00
mrg 716798baae Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors. 2020-07-13 13:01:00 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
mrg a3195c0827 Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
mrg f49448d0a7 Merge remote-tracking branch 'private/dev' into dev 2020-07-09 11:58:04 -07:00
mrg a989ea63a0 Move magic/netgen files to tech dir 2020-07-09 11:33:14 -07:00
mrg 27166c75f0 Don't remove temp files during regular openram runs. 2020-07-03 07:00:56 -07:00
mrg 5dde466ab9 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-03 06:55:45 -07:00
mrg 282f944b2f Also write .lvs file since it can be different the .sp 2020-07-03 06:55:35 -07:00
mrg ffcf762784 Merge remote-tracking branch 'private/dev' into dev 2020-07-03 06:47:37 -07:00
Hunter Nichols 206b02a7ee Merge branch 'dev' into characterizer_bug_fixes 2020-07-02 18:00:41 -07:00
Hunter Nichols fb34338fdf Removed debug statements 2020-07-02 18:00:02 -07:00
mrg 2a86f9015b Merge remote-tracking branch 'private/dev' into dev 2020-07-02 16:51:06 -07:00
Hunter Nichols 119bd94689 Fixed warnings with single port characterization. Cleaned up some signal names. 2020-07-02 15:43:23 -07:00
mrg d48f483248 Fix swapped instance bug in perimeter pins. 2020-07-01 15:10:20 -07:00
mrg bed2e36550 Simplify write mask supply via logic 2020-07-01 14:44:48 -07:00
mrg 8cd1cba818 Fix missing via in wmask driver 2020-07-01 14:44:18 -07:00
mrg c340870ba0 Channel route dout wires as well in read write ports 2020-07-01 14:44:01 -07:00
mrg bb18d05f75 Move control output via inside module instead of perimeter 2020-07-01 11:33:25 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg b07f30cb9e Missing output via in control logic 2020-06-30 16:23:07 -07:00
mrg 3379f46da1 Fail unit test, but mention if LVS passes and DRC fails. 2020-06-30 16:22:44 -07:00
mrg 0a87691176 Run Calibre LVS even if DRC fails. 2020-06-30 15:27:10 -07:00
mrg c1fedda575 Modifications for min area metal. 
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
 2020-06-30 15:07:34 -07:00