 mrg
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2643a96f97
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Order inputs wordline, bitline, supply
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2020-08-18 14:29:36 -07:00 |
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mrg
|
e37a9234cc
|
Update replica column call to new refactor
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2020-08-18 09:14:50 -07:00 |
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|
mrg
|
bc974ff78e
|
Update replica column unit tests for new refactor
|
2020-08-18 08:56:24 -07:00 |
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|
mrg
|
99e252d6d4
|
Update interface of RBL array
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2020-08-17 17:19:07 -07:00 |
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|
mrg
|
b1e55f9072
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Add local bitcell array
|
2020-08-17 15:14:42 -07:00 |
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|
mrg
|
60224b105f
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-08-17 14:20:34 -07:00 |
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mrg
|
94bfad4113
|
Horizontal gnd vias for unused array inputs
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2020-08-17 13:24:34 -07:00 |
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mrg
|
bddb251a84
|
More room for power contacts
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2020-08-17 12:32:44 -07:00 |
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mrg
|
35a1b00aa0
|
Extra space for unused wl contacts
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2020-08-14 14:23:40 -07:00 |
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|
mrg
|
170e3feb7d
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Fix order of replica wordlines and bitlines
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2020-08-14 14:14:49 -07:00 |
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mrg
|
2ac04efe2e
|
Must connect for replica cells other than top/bottom
|
2020-08-13 16:26:19 -07:00 |
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|
mrg
|
50525e70f4
|
Fix up to SRAM level with new replica bitcell array ports.
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2020-08-13 14:29:10 -07:00 |
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mrg
|
a55909930f
|
Replace replcia_bitcell_array with new one in bank
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2020-08-12 09:49:14 -07:00 |
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mrg
|
8e890c2014
|
Replica bitcell with all the fixings
|
2020-08-11 15:00:29 -07:00 |
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|
mrg
|
30976df48f
|
Change inheritance inits to use super
|
2020-08-06 11:33:26 -07:00 |
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mrg
|
eef97ff215
|
Reabstracting bit and word line names.
|
2020-08-06 11:17:49 -07:00 |
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|
mrg
|
2fa561f98f
|
Local bitcell array edits. Skip test by default.
|
2020-07-29 10:08:13 -07:00 |
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|
mrg
|
c260297366
|
Allow replica_bitcell_array without the replica columns for local wordlines.
|
2020-07-27 16:22:21 -07:00 |
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mrg
|
2991534d3f
|
Drafting local bitline stuff.
|
2020-07-23 17:15:39 -07:00 |
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mrg
|
e1967dc548
|
Draft local and global arrays. Ensure rows before cols in usage.
|
2020-07-23 14:43:14 -07:00 |
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|
mrg
|
58846a4a25
|
Limit wordline driver size. Place row addr dff near predecoders.
|
2020-07-20 17:57:38 -07:00 |
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|
mrg
|
bed2e36550
|
Simplify write mask supply via logic
|
2020-07-01 14:44:48 -07:00 |
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|
mrg
|
8cd1cba818
|
Fix missing via in wmask driver
|
2020-07-01 14:44:18 -07:00 |
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|
mrg
|
bb18d05f75
|
Move control output via inside module instead of perimeter
|
2020-07-01 11:33:25 -07:00 |
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|
mrg
|
3d0f29ff3a
|
Fix missing via LVS issues. LVS passing for some 20 tests.
|
2020-07-01 09:22:59 -07:00 |
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|
mrg
|
b07f30cb9e
|
Missing output via in control logic
|
2020-06-30 16:23:07 -07:00 |
|
|
mrg
|
011ac2fc05
|
Don't route to clk to perimeter on m2
|
2020-06-30 13:57:45 -07:00 |
|
|
mrg
|
a48ea52253
|
Add missing contact to vdd pins.
|
2020-06-30 13:26:38 -07:00 |
|
|
mrg
|
eb11ac22f3
|
Widen pitch of control bus in bank.
|
2020-06-30 10:58:09 -07:00 |
|
|
mrg
|
372a8a728e
|
Off by one error in channel spacing
|
2020-06-29 16:47:34 -07:00 |
|
|
mrg
|
459e3789b8
|
Change control layers in sky130.
|
2020-06-29 16:23:25 -07:00 |
|
|
mrg
|
bec948dcc3
|
Fix error in when to add vias for array power
|
2020-06-29 15:28:55 -07:00 |
|
|
mrg
|
07d0f3af8e
|
Only copy end-cap pins to the bank level
|
2020-06-29 11:46:59 -07:00 |
|
|
mrg
|
1bc0775810
|
Only add pins to periphery
|
2020-06-29 10:03:24 -07:00 |
|
|
mrg
|
5285468380
|
All bitcells need a vdd/gnd pin
|
2020-06-28 15:09:47 -07:00 |
|
|
mrg
|
051c8d8697
|
Only add bitcells to dummy and replica rows and columns (the perimeter)
|
2020-06-28 14:47:54 -07:00 |
|
|
mrg
|
225fc69420
|
Use preferred routing direction
|
2020-06-28 14:29:12 -07:00 |
|
|
mrg
|
0c9f52e22f
|
Realign col decoder and control by 1/4 so metal can pass over
|
2020-06-28 07:15:06 -07:00 |
|
|
mrg
|
66ea559209
|
Use channel for dffs all at once
|
2020-06-27 08:23:12 -07:00 |
|
|
mrg
|
609aa98c8b
|
Move write mask pin to left of cell to avoid sense amp
|
2020-06-27 08:21:53 -07:00 |
|
|
mrg
|
2bd498c39c
|
Change precharge layer to m3
|
2020-06-27 08:21:30 -07:00 |
|
|
mrg
|
c07e20cbe4
|
Move mux select from li to m2 in sky130
|
2020-06-26 14:27:16 -07:00 |
|
|
mrg
|
f57eeb88eb
|
PEP8 cleanup, multiple vdd/gnd support
|
2020-06-26 11:47:55 -07:00 |
|
|
mrg
|
e23d41c1d4
|
PEP8 cleanup
|
2020-06-26 11:47:35 -07:00 |
|
|
mrg
|
66df659ad4
|
Col decoders are anything not bitcell pitch.
|
2020-06-25 14:25:48 -07:00 |
|
|
mrg
|
f84ee04fa9
|
Single bank passing.
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
|
2020-06-25 14:03:59 -07:00 |
|
|
mrg
|
93d65e84e1
|
Fix power pin layer problems in delay line
|
2020-06-24 10:26:49 -07:00 |
|
 Joey Kunzler
|
4e83e8c648
|
added contact to locali for wmask
|
2020-06-23 18:13:17 -07:00 |
|
|
mrg
|
cfa234a4d0
|
Extra space between decoders for well spacing
|
2020-06-23 15:39:42 -07:00 |
|
|
mrg
|
cd23b31ab4
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-06-22 12:55:45 -07:00 |
|