mrg 2991534d3f Drafting local bitline stuff.

2020-07-23 17:15:39 -07:00

..

bank_select.py

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

bank.py

Limit wordline driver size. Place row addr dff near predecoders.

2020-07-20 17:57:38 -07:00

bitcell_array.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

bitcell_base_array.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

col_cap_array.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

control_logic.py

Move control output via inside module instead of perimeter

2020-07-01 11:33:25 -07:00

delay_chain.py

Fix missing via LVS issues. LVS passing for some 20 tests.

2020-07-01 09:22:59 -07:00

dff_array.py

Add missing contact to vdd pins.

2020-06-30 13:26:38 -07:00

dff_buf_array.py

Add missing contact to vdd pins.

2020-06-30 13:26:38 -07:00

dff_buf.py

DRC and LVS fixes for pinv_dec

2020-06-12 15:23:51 -07:00

dff_inv_array.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dff_inv.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dummy_array.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

global_bitcell_array.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

hierarchical_decoder.py

Limit wordline driver size. Place row addr dff near predecoders.

2020-07-20 17:57:38 -07:00

hierarchical_predecode2x4.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

hierarchical_predecode3x8.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

hierarchical_predecode4x16.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

hierarchical_predecode.py

Col decoders are anything not bitcell pitch.

2020-06-25 14:25:48 -07:00

local_bitcell_array.py

Drafting local bitline stuff.

2020-07-23 17:15:39 -07:00

module_type.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

multibank.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

port_address.py

Limit wordline driver size. Place row addr dff near predecoders.

2020-07-20 17:57:38 -07:00

port_data.py

Fix missing via in wmask driver

2020-07-01 14:44:18 -07:00

precharge_array.py

Change control layers in sky130.

2020-06-29 16:23:25 -07:00

replica_bitcell_array.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

replica_column.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

row_cap_array.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

sense_amp_array.py

Change control layers in sky130.

2020-06-29 16:23:25 -07:00

sense_amp.py

PEP8 cleanup

2020-06-26 11:47:35 -07:00

single_level_column_mux_array.py

Change control layers in sky130.

2020-06-29 16:23:25 -07:00

tri_gate_array.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

wordline_buffer_array.py

Drafting local bitline stuff.

2020-07-23 17:15:39 -07:00

wordline_driver_array.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

write_driver_array.py

Move write mask pin to left of cell to avoid sense amp

2020-06-27 08:21:53 -07:00

write_mask_and_array.py

Simplify write mask supply via logic

2020-07-01 14:44:48 -07:00