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bank.py
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Fix up to SRAM level with new replica bitcell array ports.
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2020-08-13 14:29:10 -07:00 |
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bank_select.py
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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bitcell_array.py
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Reabstracting bit and word line names.
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2020-08-06 11:17:49 -07:00 |
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bitcell_base_array.py
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Reabstracting bit and word line names.
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2020-08-06 11:17:49 -07:00 |
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col_cap_array.py
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Allow replica_bitcell_array without the replica columns for local wordlines.
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2020-07-27 16:22:21 -07:00 |
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control_logic.py
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Move control output via inside module instead of perimeter
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2020-07-01 11:33:25 -07:00 |
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delay_chain.py
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Fix missing via LVS issues. LVS passing for some 20 tests.
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2020-07-01 09:22:59 -07:00 |
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dff_array.py
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Add missing contact to vdd pins.
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2020-06-30 13:26:38 -07:00 |
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dff_buf.py
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DRC and LVS fixes for pinv_dec
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2020-06-12 15:23:51 -07:00 |
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dff_buf_array.py
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Add missing contact to vdd pins.
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2020-06-30 13:26:38 -07:00 |
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dff_inv.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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dff_inv_array.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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dummy_array.py
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Draft local and global arrays. Ensure rows before cols in usage.
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2020-07-23 14:43:14 -07:00 |
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global_bitcell_array.py
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Draft local and global arrays. Ensure rows before cols in usage.
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2020-07-23 14:43:14 -07:00 |
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hierarchical_decoder.py
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Limit wordline driver size. Place row addr dff near predecoders.
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2020-07-20 17:57:38 -07:00 |
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hierarchical_predecode.py
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Col decoders are anything not bitcell pitch.
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2020-06-25 14:25:48 -07:00 |
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hierarchical_predecode2x4.py
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Thin-cell decoder changes.
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2020-05-29 10:36:07 -07:00 |
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hierarchical_predecode3x8.py
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Thin-cell decoder changes.
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2020-05-29 10:36:07 -07:00 |
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hierarchical_predecode4x16.py
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Thin-cell decoder changes.
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2020-05-29 10:36:07 -07:00 |
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local_bitcell_array.py
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Replica bitcell with all the fixings
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2020-08-11 15:00:29 -07:00 |
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module_type.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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multibank.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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port_address.py
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Limit wordline driver size. Place row addr dff near predecoders.
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2020-07-20 17:57:38 -07:00 |
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port_data.py
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Fix missing via in wmask driver
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2020-07-01 14:44:18 -07:00 |
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precharge_array.py
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Change control layers in sky130.
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2020-06-29 16:23:25 -07:00 |
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replica_bitcell_array.py
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Fix up to SRAM level with new replica bitcell array ports.
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2020-08-13 14:29:10 -07:00 |
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replica_column.py
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Replica bitcell with all the fixings
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2020-08-11 15:00:29 -07:00 |
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row_cap_array.py
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Allow replica_bitcell_array without the replica columns for local wordlines.
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2020-07-27 16:22:21 -07:00 |
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sense_amp.py
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PEP8 cleanup
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2020-06-26 11:47:35 -07:00 |
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sense_amp_array.py
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Change control layers in sky130.
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2020-06-29 16:23:25 -07:00 |
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single_level_column_mux_array.py
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Change control layers in sky130.
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2020-06-29 16:23:25 -07:00 |
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tri_gate_array.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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wordline_buffer_array.py
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Replica bitcell with all the fixings
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2020-08-11 15:00:29 -07:00 |
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wordline_driver_array.py
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Draft local and global arrays. Ensure rows before cols in usage.
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2020-07-23 14:43:14 -07:00 |
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write_driver_array.py
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Move write mask pin to left of cell to avoid sense amp
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2020-06-27 08:21:53 -07:00 |
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write_mask_and_array.py
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Simplify write mask supply via logic
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2020-07-01 14:44:48 -07:00 |
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