OpenRAM/compiler/modules
mrg bb18d05f75 Move control output via inside module instead of perimeter 2020-07-01 11:33:25 -07:00
..
bank.py Widen pitch of control bus in bank. 2020-06-30 10:58:09 -07:00
bank_select.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
bitcell_array.py Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00
bitcell_base_array.py All bitcells need a vdd/gnd pin 2020-06-28 15:09:47 -07:00
col_cap_array.py PEP8 formatting 2020-06-22 12:55:18 -07:00
control_logic.py Move control output via inside module instead of perimeter 2020-07-01 11:33:25 -07:00
delay_chain.py Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
dff_array.py Add missing contact to vdd pins. 2020-06-30 13:26:38 -07:00
dff_buf.py DRC and LVS fixes for pinv_dec 2020-06-12 15:23:51 -07:00
dff_buf_array.py Add missing contact to vdd pins. 2020-06-30 13:26:38 -07:00
dff_inv.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dff_inv_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dummy_array.py Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
hierarchical_decoder.py Col decoders are anything not bitcell pitch. 2020-06-25 14:25:48 -07:00
hierarchical_predecode.py Col decoders are anything not bitcell pitch. 2020-06-25 14:25:48 -07:00
hierarchical_predecode2x4.py Thin-cell decoder changes. 2020-05-29 10:36:07 -07:00
hierarchical_predecode3x8.py Thin-cell decoder changes. 2020-05-29 10:36:07 -07:00
hierarchical_predecode4x16.py Thin-cell decoder changes. 2020-05-29 10:36:07 -07:00
module_type.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
multibank.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
port_address.py Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
port_data.py Change s8 to sky130 2020-06-12 14:23:26 -07:00
precharge_array.py Change control layers in sky130. 2020-06-29 16:23:25 -07:00
replica_bitcell_array.py Fix error in when to add vias for array power 2020-06-29 15:28:55 -07:00
replica_column.py Fix error in when to add vias for array power 2020-06-29 15:28:55 -07:00
row_cap_array.py PEP8 formatting 2020-06-22 12:55:18 -07:00
sense_amp.py PEP8 cleanup 2020-06-26 11:47:35 -07:00
sense_amp_array.py Change control layers in sky130. 2020-06-29 16:23:25 -07:00
single_level_column_mux_array.py Change control layers in sky130. 2020-06-29 16:23:25 -07:00
tri_gate_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
wordline_driver_array.py Change s8 to sky130 2020-06-12 14:23:26 -07:00
write_driver_array.py Move write mask pin to left of cell to avoid sense amp 2020-06-27 08:21:53 -07:00
write_mask_and_array.py Use channel for dffs all at once 2020-06-27 08:23:12 -07:00