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159 Commits

Author SHA1 Message Date
Akash Levy 96104b4431 Merge branch 'main' into sat_clkgate 2026-03-03 20:57:42 -08:00
Akash Levy 958f1c608a
Merge pull request #116 from Silimate/autoscope 
Autoscope
 2026-03-03 20:49:13 -08:00
tondapusili b438fd1fe9 negopt: fix quadratic blowup by adding index hints and deferring nusers to filter 2026-03-02 19:33:25 -08:00
Stan Lee da25b800bc finalized 2026-03-02 11:05:44 -08:00
Stan Lee c459a74c13 autoscoping 2026-03-01 15:39:35 -08:00
Akash Levy 7a35a982d3
Merge pull request #111 from Silimate/timing_balance_impl 
silimate: add opt_timing_balance pass and tests
 2026-02-28 12:22:23 -08:00
Advay Singh 8974f3473f
Update passes/silimate/infer_ce.cc 
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
 2026-02-27 12:37:49 -08:00
AdvaySingh1 3cee420bf9 Merge branch 'main' into sat_clkgate 2026-02-27 11:15:22 -08:00
tondapusili f46b8d2a44 silimate: add opt_timing_balance pass and tests 2026-02-27 09:13:39 -08:00
tondapusili 2f276d0723 Added log flushes after each negopt pass for clearer logging 2026-02-25 12:15:46 -08:00
AdvaySingh1 5e58bf22e0 Changed param naming for consistancy 2026-02-19 09:42:59 -08:00
AdvaySingh1 ee896b9eee Removed sorting of similar candidate_gates for unnessessary optimization 2026-02-18 09:08:25 -08:00
AdvaySingh1 6cb9fadded Removed downstream signals causing equiv_opt failures due to feedback loop 2026-02-17 16:22:59 -08:00
AdvaySingh1 90dbb91cae Changed min cone size 2026-02-17 16:22:05 -08:00
AdvaySingh1 2ab89e1146 Passing equiv_opt pass and speed boosts 2026-02-17 16:13:51 -08:00
AdvaySingh1 c8b6869e65 Removed optimizations from infer_ce.cc for profiling 2026-02-17 15:20:57 -08:00
AdvaySingh1 a8e4fccc56 Removed simulation and isValidGatingSignal function 2026-02-17 14:07:22 -08:00
AdvaySingh1 fa9e7a77d7 Removed normal clockgate pass options form sate_clockgate pass 2026-02-17 13:43:22 -08:00
AdvaySingh1 efcabb270f Added caching of simulation runs for speed 2026-02-17 13:38:32 -08:00
AdvaySingh1 499e83a549 Switched to using CE module. Mostly retaining SAT gates. Still needs speedup 2026-02-17 12:41:59 -08:00
AdvaySingh1 e755f6c42e Added initial simulation. Incorrect simulation -- changed the number of accedpted results as well as increasing runtime 2026-02-17 12:14:53 -08:00
AdvaySingh1 2212d85626 Changed configurations to match the OpenROAD project 2026-02-17 11:57:56 -08:00
AdvaySingh1 144db54c4e Changed to inverse hashing for more flexibility 2026-02-17 11:53:06 -08:00
AdvaySingh1 f0de3ae8de Initial sat_clockgate pass pre speed optimization 2026-02-17 11:19:18 -08:00
AdvaySingh1 cc6605f8e2 Added passing on the args into the clockgate pass so there's an icg cell for the mapping 2026-02-17 10:49:18 -08:00
AdvaySingh1 2ab34262ec Added profiling info before and after sat_clockgate pass 2026-02-17 09:23:32 -08:00
AdvaySingh1 3567960671 Changed hashing from string to pair with vector and bool 2026-02-13 17:01:58 -08:00
AdvaySingh1 5ce8aada27 Added profiling for literal count 2026-02-13 16:34:15 -08:00
AdvaySingh1 3442bc3a85 Changed indexing to be based on the literal ID in EZSat and sorted to allow better hashing 2026-02-13 16:15:31 -08:00
AdvaySingh1 80fbdf7e6a Removed duplication of vectors and called clockgate pass post creating enable signals 2026-02-13 15:33:45 -08:00
AdvaySingh1 feffbbe32c Added initial impl based on OpenROAD 2026-02-12 16:12:50 -08:00
AdvaySingh1 514c01efd2 Added prune expressions list TODO 2026-02-12 12:14:25 -08:00
AdvaySingh1 745f17a34e Changed input_set_is_enable_exact to XOR Mitter 2026-02-12 11:10:10 -08:00
AdvaySingh1 532d1d45a8 Resolved adding SigBits from Q using static EXCLUDE_Q_FROM_ENABLE knob 2026-02-11 15:08:49 -08:00
AdvaySingh1 4ca4392e9b Simplied recursion in sat_clockgate pass 2026-02-11 14:56:46 -08:00
AdvaySingh1 dd3f2e370c Fixed naming for bfs_find_potential_enable_inputs 2026-02-11 12:31:13 -08:00
AdvaySingh1 5b384511f2 Added initial SatClockgateWorker 2026-02-11 11:02:15 -08:00
AdvaySingh1 b4cd82bacf Added initial printing of the clocks with dump_flipflops_to_file 2026-02-11 10:56:07 -08:00
AdvaySingh1 6ad01fa850 Added initial pass structure 2026-02-10 14:33:37 -08:00
AdvaySingh1 b53acb0ff0 Added pass in Makefile.inc 2026-02-10 14:33:17 -08:00
AdvaySingh1 b4ef420c3f Added inital SAT based clock gating file 2026-02-10 14:02:15 -08:00
Akash Levy ee46f498e1
Update negopt.cc 2026-02-07 17:54:16 -08:00
tondapusili 6bb43f109c fixed edge cases in negopt passes, fixed cell naming inconsistencies 2026-02-06 16:38:55 -08:00
tondapusili d592f312ab mux_push implementation 2026-02-05 16:49:59 -08:00
tondapusili 643427d9c9 Add negopt pass with comprehensive pattern matching 
This commit introduces the negopt pass with pre/post optimization modes
for handling negation patterns in arithmetic circuits.

Pre-optimization patterns (expose for tree balancing):
- manual2sub: (a + ~b) + 1 → a - b
- sub2neg: a - b → a + (-b)
- negexpand: -(a + b) → (-a) + (-b) [with output width fix]
- negneg: -(-a) → a
- negmux: -(s ? a : b) → s ? (-a) : (-b)

Post-optimization patterns (cleanup/rebuild):
- negrebuild: (-a) + (-b) → -(a + b)
- muxneg: s ? (-a) : (-b) → -(s ? a : b)
- neg2sub: a + (-b) → a - b

All patterns use nusers() for fanout checking (standard Yosys style).
Comprehensive test coverage with positive/negative cases and formal
verification via equiv_opt.
 2026-02-03 17:21:21 -08:00
Akash Levy 4e937450b4
Merge pull request #97 from Silimate/reg-rename 
Bug fix for reg_rename pass
 2026-01-28 19:08:26 -08:00
Stan Lee c0a1529eb8 reduce verbosity 2026-01-28 18:05:21 -08:00
Akash Levy e8d27892f0
Merge pull request #96 from Silimate/fanoutbuf_src_attr 
Changed fanoutbuf.cc to include src attributes on buffers connected t…
 2026-01-28 17:50:46 -08:00
Stan Lee 04faedd131 syntax err 2026-01-28 17:40:57 -08:00
Stan Lee dfef18010d shorter lines 2026-01-28 17:20:19 -08:00