mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #111 from Silimate/timing_balance_impl
silimate: add opt_timing_balance pass and tests
This commit is contained in:
Akash Levy
GitHub
commit
7a35a982d3
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@ -35,14 +35,14 @@ runs:
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if: runner.os == 'Linux'
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uses: awalsh128/cache-apt-pkgs-action@v1.6.0
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with:
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||||
packages: gawk git make python3 bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libnsl-dev libdwarf-dev libelf-dev elfutils libdw-dev ccache
|
||||
packages: gawk git make python3 bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libnsl-dev libdwarf-dev libelf-dev elfutils libdw-dev ccache
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version: ${{ inputs.runs-on }}-commonys
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- name: Linux build dependencies
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if: runner.os == 'Linux' && inputs.get-build-deps == 'true'
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uses: awalsh128/cache-apt-pkgs-action@v1.6.0
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||||
with:
|
||||
packages: bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libgtest-dev
|
||||
packages: gawk git make python3 bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libnsl-dev libdwarf-dev libelf-dev elfutils libdw-dev ccache libgtest-dev
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version: ${{ inputs.runs-on }}-buildys
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- name: Linux docs dependencies
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@ -116,7 +116,7 @@ jobs:
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uses: ./.github/actions/setup-build-env
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with:
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runs-on: ${{ matrix.os }}
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get-test-deps: true
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get-build-deps: true
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get-iverilog: true
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- name: Download build artifact
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@ -13,6 +13,7 @@ OBJS += passes/silimate/reg_rename.o
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OBJS += passes/silimate/splitfanout.o
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OBJS += passes/silimate/splitlarge.o
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OBJS += passes/silimate/splitnetlist.o
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OBJS += passes/silimate/opt_timing_balance.o
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OBJS += passes/silimate/opt_expand.o
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GENFILES += passes/silimate/peepopt_expand.h
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,511 @@
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#
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# opt_timing_balance regression coverage
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#
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# ---------------------------------------------------------------------------
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# Case: XOR chain with late leaf should be rewritten
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: xor late leaf rewrite"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] u0,
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input wire [7:0] u1,
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input wire [15:0] a,
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input wire [15:0] b,
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input wire [15:0] c,
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input wire [15:0] d,
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output wire [15:0] y
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);
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wire [15:0] late = u0 * u1;
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assign y = late ^ a ^ b ^ c ^ d;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_timing_balance -logic
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design -load postopt
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select -assert-count 4 t:$xor
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select o:y %ci2 t:$xor %i -set root_xor
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select @root_xor i:late -assert-count 1
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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# Case: Default mode should rewrite both logic and arithmetic cones
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: default mode mixed categories"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] u0,
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input wire [7:0] u1,
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input wire [7:0] u2,
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input wire [7:0] u3,
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input wire [15:0] a,
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input wire [15:0] b,
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input wire [15:0] c,
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input wire [15:0] d,
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output wire [15:0] y_add,
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output wire [15:0] y_xor
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);
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wire [15:0] late_add = u0 * u1;
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wire [15:0] late_xor = u2 * u3;
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assign y_add = late_add + a + b + c + d;
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assign y_xor = late_xor ^ a ^ b ^ c ^ d;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_timing_balance
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design -load postopt
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select -assert-min 1 t:$add a:timing_balance_generated=1 %i
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select -assert-min 1 t:$xor a:timing_balance_generated=1 %i
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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# Case: Running the pass twice should be idempotent on generated cones
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: idempotent second invocation"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] u0,
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input wire [7:0] u1,
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input wire [15:0] a,
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input wire [15:0] b,
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input wire [15:0] c,
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input wire [15:0] d,
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output wire [15:0] y
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);
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wire [15:0] late = u0 * u1;
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assign y = late + a + b + c + d;
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endmodule
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EOF
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check -assert
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opt_timing_balance -arith
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select -assert-count 4 t:$add a:timing_balance_generated=1 %i
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opt_timing_balance -arith
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select -assert-count 4 t:$add a:timing_balance_generated=1 %i
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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# Case: Without negopt -pre, subtraction chains should not be rewritten
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: direct subtraction conservative skip"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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input wire [7:0] c,
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input wire [7:0] d,
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output wire [7:0] y
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);
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assign y = a - b - c - d;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_timing_balance -arith
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design -load postopt
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select -assert-count 3 t:$sub
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select -assert-count 0 t:$add a:timing_balance_generated=1 %i
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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# Case: Signed-width logic extension semantics are preserved under rewrite
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: signed logic extension equivalence"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] u0,
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input wire [7:0] u1,
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input wire signed [1:0] a,
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input wire [3:0] b,
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input wire [3:0] c,
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output wire [3:0] y
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);
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wire [3:0] late = u0 * u1;
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assign y = late & a & b & c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_timing_balance -logic
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design -load postopt
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select -assert-min 1 t:$and a:timing_balance_generated=1 %i
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select o:y %ci2 t:$and %i -set signed_logic_root
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select @signed_logic_root i:late -assert-count 1
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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# Case: AND chain with late leaf should be rewritten
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: and late leaf rewrite"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] u0,
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input wire [7:0] u1,
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input wire [15:0] a,
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input wire [15:0] b,
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input wire [15:0] c,
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input wire [15:0] d,
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output wire [15:0] y
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);
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wire [15:0] late = u0 * u1;
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assign y = late & a & b & c & d;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_timing_balance -logic
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design -load postopt
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select -assert-count 4 t:$and
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select o:y %ci2 t:$and %i -set root_and
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select @root_and i:late -assert-count 1
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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# Case: OR chain with late leaf should be rewritten
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: or late leaf rewrite"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] u0,
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input wire [7:0] u1,
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input wire [15:0] a,
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input wire [15:0] b,
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input wire [15:0] c,
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input wire [15:0] d,
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output wire [15:0] y
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);
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wire [15:0] late = u0 * u1;
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assign y = late | a | b | c | d;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_timing_balance -logic
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design -load postopt
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select -assert-count 4 t:$or
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select o:y %ci2 t:$or %i -set root_or
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select @root_or i:late -assert-count 1
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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# Case: ADD chain with late leaf should be rewritten
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: add late leaf rewrite"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] u0,
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input wire [7:0] u1,
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input wire [15:0] a,
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input wire [15:0] b,
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input wire [15:0] c,
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input wire [15:0] d,
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output wire [15:0] y
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);
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wire [15:0] late = u0 * u1;
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assign y = late + a + b + c + d;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_timing_balance -arith
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design -load postopt
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select -assert-count 4 t:$add
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select o:y %ci2 t:$add %i -set root_add
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select @root_add i:late -assert-count 1
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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# Case: Balanced add tree should remain unchanged (no rewrite)
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: balanced add no-op"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [15:0] a,
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input wire [15:0] b,
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input wire [15:0] c,
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input wire [15:0] d,
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input wire [15:0] e,
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input wire [15:0] f,
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input wire [15:0] g,
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input wire [15:0] h,
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output wire [15:0] y
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);
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assign y = ((a+b)+(c+d))+((e+f)+(g+h));
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_timing_balance -arith
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design -load postopt
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select -assert-count 7 t:$add
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select -assert-count 0 t:$add a:timing_balance_generated=1 %i
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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# Case: -logic mode must not rewrite arithmetic cones
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# ---------------------------------------------------------------------------
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log -header "opt_timing_balance: mode filter logic-only"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] u0,
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input wire [7:0] u1,
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input wire [15:0] a,
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input wire [15:0] b,
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input wire [15:0] c,
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input wire [15:0] d,
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output wire [15:0] y
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);
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wire [15:0] late = u0 * u1;
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assign y = late + a + b + c + d;
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endmodule
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EOF
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check -assert
|
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|
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equiv_opt -assert opt_timing_balance -logic
|
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design -load postopt
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select -assert-count 4 t:$add
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select -assert-count 0 t:$add a:timing_balance_generated=1 %i
|
||||
|
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design -reset
|
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log -pop
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|
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# ---------------------------------------------------------------------------
|
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# Case: -arith mode must not rewrite logic cones
|
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# ---------------------------------------------------------------------------
|
||||
log -header "opt_timing_balance: mode filter arith-only"
|
||||
log -push
|
||||
design -reset
|
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read_verilog <<EOF
|
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module top (
|
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input wire [7:0] u0,
|
||||
input wire [7:0] u1,
|
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input wire [15:0] a,
|
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input wire [15:0] b,
|
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input wire [15:0] c,
|
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input wire [15:0] d,
|
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output wire [15:0] y
|
||||
);
|
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wire [15:0] late = u0 * u1;
|
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assign y = late ^ a ^ b ^ c ^ d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
equiv_opt -assert opt_timing_balance -arith
|
||||
design -load postopt
|
||||
select -assert-count 4 t:$xor
|
||||
select -assert-count 0 t:$xor a:timing_balance_generated=1 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# Case: Shared-fanout cone must preserve both tap and final output semantics
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "opt_timing_balance: shared fanout tap safety"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [15:0] a,
|
||||
input wire [15:0] b,
|
||||
input wire [15:0] c,
|
||||
input wire [15:0] d,
|
||||
output wire [15:0] tap,
|
||||
output wire [15:0] y
|
||||
);
|
||||
wire [15:0] x0 = a + b;
|
||||
wire [15:0] x1 = x0 + c;
|
||||
assign tap = x1;
|
||||
assign y = x1 + d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
equiv_opt -assert opt_timing_balance -arith
|
||||
design -load postopt
|
||||
select o:tap %ci2 t:$add %i -assert-count 1
|
||||
select o:y %ci2 t:$add %i -assert-count 1
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# Case: Subtraction chain after negopt -pre should be balanced as add/neg
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "opt_timing_balance: negopt-pre normalized subtraction chain"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [7:0] c,
|
||||
input wire [7:0] d,
|
||||
output wire [7:0] y
|
||||
);
|
||||
assign y = a - b - c - d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
negopt -pre
|
||||
select -assert-count 0 t:$sub
|
||||
equiv_opt -assert opt_timing_balance -arith
|
||||
design -load postopt
|
||||
select -assert-min 1 t:$add a:timing_balance_generated=1 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# Case: Mixed-sign add chains should be skipped conservatively
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "opt_timing_balance: mixed-sign conservative skip"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire signed [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [7:0] c,
|
||||
output wire [8:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
equiv_opt -assert opt_timing_balance -arith
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$add
|
||||
select -assert-count 0 t:$add a:timing_balance_generated=1 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# Case: Two independent arithmetic heads should both rewrite
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "opt_timing_balance: multi-head arithmetic rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] u0,
|
||||
input wire [7:0] u1,
|
||||
input wire [7:0] u2,
|
||||
input wire [7:0] u3,
|
||||
input wire [15:0] a,
|
||||
input wire [15:0] b,
|
||||
input wire [15:0] c,
|
||||
input wire [15:0] d,
|
||||
input wire [15:0] e,
|
||||
input wire [15:0] f,
|
||||
input wire [15:0] g,
|
||||
input wire [15:0] h,
|
||||
output wire [15:0] y0,
|
||||
output wire [15:0] y1
|
||||
);
|
||||
wire [15:0] late0 = u0 * u1;
|
||||
wire [15:0] late1 = u2 * u3;
|
||||
assign y0 = late0 + a + b + c + d;
|
||||
assign y1 = late1 + e + f + g + h;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
equiv_opt -assert opt_timing_balance -arith
|
||||
design -load postopt
|
||||
select -assert-min 2 t:$add
|
||||
select o:y0 %ci2 t:$add %i -set root0
|
||||
select o:y1 %ci2 t:$add %i -set root1
|
||||
select @root0 i:late0 -assert-count 1
|
||||
select @root1 i:late1 -assert-count 1
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# Case: Generated-cell tagging exists for rewritten cones (contract test)
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "opt_timing_balance: generated tag contract"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] u0,
|
||||
input wire [7:0] u1,
|
||||
input wire [15:0] a,
|
||||
input wire [15:0] b,
|
||||
input wire [15:0] c,
|
||||
input wire [15:0] d,
|
||||
output wire [15:0] y
|
||||
);
|
||||
wire [15:0] late = u0 * u1;
|
||||
assign y = late + a + b + c + d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
equiv_opt -assert opt_timing_balance -arith
|
||||
design -load postopt
|
||||
select -assert-min 1 t:$add a:timing_balance_generated=1 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Reference in New Issue