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Added initial printing of the clocks with dump_flipflops_to_file

This commit is contained in:
AdvaySingh1 2026-02-11 10:56:07 -08:00
parent 5aeb19fb66
commit b4cd82bacf
1 changed files with 48 additions and 4 deletions
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52
passes/silimate/sat_clockgate.cc
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@ -19,19 +19,50 @@
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/ff.h"
#include <fstream>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
void dump_flipflops_to_file(RTLIL::Design *design, const std::string &filename)
{
std::ofstream outfile(filename);
if (!outfile.is_open()) {
log_error("Cannot open file %s for writing\n", filename.c_str());
return;
}
for (auto module : design->selected_modules()) {
outfile << "Module: " << log_id(module) << "\n";
log("Module: %s\n", log_id(module));
for (auto cell : module->cells()) {
if (cell->is_builtin_ff()) {
outfile << " FF: " << log_id(cell) << " (type: " << log_id(cell->type) << ")\n";
log(" FF: %s (type: %s)\n", log_id(cell), log_id(cell->type));
}
}
outfile << "\n";
}
outfile.close();
log("Wrote flip-flop list to %s\n", filename.c_str());
}
struct SatClockgatePass : public Pass {
SatClockgatePass() : Pass("sat_clockgate", "SAT-based clock gating analysis") { }
SatClockgatePass() : Pass("sat_clockgate", "SAT-based inferred clock gating") { }
void help() override
{
log("\n");
log(" sat_clockgate [selection]\n");
log(" sat_clockgate [options] [selection]\n");
log("\n");
log("This command performs SAT-based clock gating analysis.\n");
log("This command performs SAT-based inferred clock gating insertion.\n");
log("\n");
log(" -threshold <n>\n");
log(" minimum number of clock cycles that must match for clock gating\n");
log(" to be inserted (default: 1)\n");
log("\n");
}
@ -39,16 +70,29 @@ struct SatClockgatePass : public Pass {
{
log_header(design, "Executing SAT_CLOCKGATE pass.\n");
int threshold = 1;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
// Parse options here
if (args[argidx] == "-threshold" && argidx+1 < args.size()) {
threshold = std::stoi(args[++argidx]);
continue;
}
break;
}
extra_args(args, argidx, design);
log("Using threshold: %d\n", threshold);
// Dump all flip-flops to file
dump_flipflops_to_file(design, "flip_flops.txt");
for (auto module : design->selected_modules()) {
log("Processing module %s...\n", log_id(module));
// TODO: Implement SAT-based clock gating logic
// Example: calling SAT pass
// Pass::call(design, stringf("sat -verify -prove <signal> 1 %s", log_id(module)));
}
}
} SatClockgatePass;