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Removed downstream signals causing equiv_opt failures due to feedback loop

This commit is contained in:
AdvaySingh1 2026-02-17 16:22:59 -08:00
parent 90dbb91cae
commit 6cb9fadded
1 changed files with 0 additions and 34 deletions
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34
passes/silimate/infer_ce.cc
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@ -82,40 +82,6 @@ struct InferCeWorker
}
}
// Get downstream signals from a register (BFS forward through combinational logic)
pool<SigBit> getDownstreamSignals(Cell *reg, int limit)
{
pool<SigBit> visited;
std::queue<SigBit> worklist;
FfData ff(nullptr, reg);
for (auto bit : sigmap(ff.sig_q))
if (bit.wire) {
worklist.push(bit);
visited.insert(bit);
}
while (!worklist.empty() && (int)visited.size() < limit) {
SigBit bit = worklist.front();
worklist.pop();
for (auto sink_cell : sig_to_sinks[bit]) {
if (sink_cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
ID($dffsre), ID($_DFF_P_), ID($_DFF_N_)))
continue;
for (auto &conn : sink_cell->connections())
if (sink_cell->output(conn.first))
for (auto out_bit : sigmap(conn.second))
if (out_bit.wire && !visited.count(out_bit)) {
visited.insert(out_bit);
worklist.push(out_bit);
}
}
}
return visited;
}
// Get upstream signals feeding into given signals (BFS backward)
pool<SigBit> getUpstreamSignals(const pool<SigBit> &start_signals, int limit)