mirror of https://github.com/YosysHQ/yosys.git
Changed param naming for consistancy
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d84e56ecac
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5e58bf22e0
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@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
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// Configuration
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static const int DEFAULT_MAX_COVER = 100; // Max candidate signals to consider
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static const int DEFAULT_MIN_REGS = 10; // Min registers per clock gate
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static const int DEFAULT_MIN_NET_SIZE = 10; // Min registers per clock gate
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struct InferCeWorker
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{
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@ -37,7 +37,7 @@ struct InferCeWorker
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// Configuration
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int max_cover;
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int min_regs;
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int min_net_size;
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// Maps output signal bits to their driver cells
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dict<SigBit, Cell*> sig_to_driver;
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@ -53,9 +53,9 @@ struct InferCeWorker
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int rejected_sat_count = 0;
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int sat_solves = 0;
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InferCeWorker(Module *module, int max_cover, int min_regs)
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InferCeWorker(Module *module, int max_cover, int min_net_size)
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: module(module), sigmap(module),
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max_cover(max_cover), min_regs(min_regs)
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max_cover(max_cover), min_net_size(min_net_size)
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{
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// Build driver and sink maps
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for (auto cell : module->cells()) {
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@ -481,7 +481,7 @@ struct InferCeWorker
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// Insert clock gates for groups meeting threshold
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for (auto &gate : accepted_gates) {
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if ((int)gate.regs.size() >= min_regs) {
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if ((int)gate.regs.size() >= min_net_size) {
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insertClockGate(gate.regs, gate.conds, gate.is_enable);
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accepted_count += gate.regs.size();
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}
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@ -509,9 +509,9 @@ struct InferCePass : public Pass {
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log(" maximum number of candidate signals to consider per register\n");
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log(" (default: %d)\n", DEFAULT_MAX_COVER);
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log("\n");
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log(" -min_regs <n>\n");
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log(" -min_net_size <n>\n");
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log(" minimum number of registers that must share a gating condition\n");
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log(" for a clock gate to be inserted (default: %d)\n", DEFAULT_MIN_REGS);
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log(" for a clock gate to be inserted (default: %d)\n", DEFAULT_MIN_NET_SIZE);
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log("\n");
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}
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@ -520,7 +520,7 @@ struct InferCePass : public Pass {
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log_header(design, "Executing INFER_CE pass.\n");
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int max_cover = DEFAULT_MAX_COVER;
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int min_regs = DEFAULT_MIN_REGS;
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int min_net_size = DEFAULT_MIN_NET_SIZE;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -528,8 +528,8 @@ struct InferCePass : public Pass {
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max_cover = std::stoi(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-min_regs" && argidx+1 < args.size()) {
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min_regs = std::stoi(args[++argidx]);
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if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
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min_net_size = std::stoi(args[++argidx]);
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continue;
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}
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break;
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@ -538,7 +538,7 @@ struct InferCePass : public Pass {
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int total_gates = 0;
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for (auto module : design->selected_modules()) {
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InferCeWorker worker(module, max_cover, min_regs);
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InferCeWorker worker(module, max_cover, min_net_size);
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worker.run();
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total_gates += worker.accepted_count;
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}
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