mirror of https://github.com/YosysHQ/yosys.git
Passing equiv_opt pass and speed boosts
This commit is contained in:
AdvaySingh1
parent
c8b6869e65
commit
2ab89e1146
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@ -22,77 +22,10 @@
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#include "kernel/satgen.h"
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#include <queue>
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#include <algorithm>
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#include <fstream>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Profile all flip-flops and write to file
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void profileFlipFlops(Module *module, const std::string &filename, const std::string &label)
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{
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std::ofstream out(filename, std::ios::app);
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out << "\n=== " << label << " ===\n";
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out << "Module: " << log_id(module) << "\n\n";
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int total_ffs = 0;
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int ffs_with_ce = 0;
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int ffs_with_arst = 0;
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int ffs_with_srst = 0;
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int total_bits = 0;
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int bits_with_ce = 0;
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for (auto cell : module->cells()) {
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if (!cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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continue;
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FfData ff(nullptr, cell);
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total_ffs++;
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total_bits += ff.width;
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out << "FF: " << log_id(cell) << "\n";
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out << " type: " << log_id(cell->type) << "\n";
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out << " width: " << ff.width << "\n";
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out << " has_clk: " << (ff.has_clk ? "yes" : "no") << "\n";
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out << " has_ce: " << (ff.has_ce ? "yes" : "no");
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if (ff.has_ce) {
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out << " (sig_ce: " << log_signal(ff.sig_ce) << ", pol: " << (ff.pol_ce ? "active-high" : "active-low") << ")";
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ffs_with_ce++;
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bits_with_ce += ff.width;
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}
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out << "\n";
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out << " has_arst: " << (ff.has_arst ? "yes" : "no");
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if (ff.has_arst) {
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out << " (sig_arst: " << log_signal(ff.sig_arst) << ")";
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ffs_with_arst++;
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}
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out << "\n";
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out << " has_srst: " << (ff.has_srst ? "yes" : "no");
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if (ff.has_srst) {
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out << " (sig_srst: " << log_signal(ff.sig_srst) << ")";
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ffs_with_srst++;
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}
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out << "\n";
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out << " sig_clk: " << log_signal(ff.sig_clk) << "\n";
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out << " sig_d: " << log_signal(ff.sig_d) << "\n";
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out << " sig_q: " << log_signal(ff.sig_q) << "\n";
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out << "\n";
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}
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out << "--- Summary ---\n";
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out << "Total FFs: " << total_ffs << "\n";
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out << "Total bits: " << total_bits << "\n";
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out << "FFs with CE: " << ffs_with_ce << " (" << (total_ffs ? 100*ffs_with_ce/total_ffs : 0) << "%)\n";
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out << "Bits with CE: " << bits_with_ce << " (" << (total_bits ? 100*bits_with_ce/total_bits : 0) << "%)\n";
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out << "FFs with ARST: " << ffs_with_arst << "\n";
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out << "FFs with SRST: " << ffs_with_srst << "\n";
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out << "\n";
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out.close();
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}
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// Configuration
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static const int DEFAULT_MAX_COVER = 100; // Max candidate signals to consider
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static const int DEFAULT_MIN_REGS = 10; // Min registers per clock gate
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@ -109,21 +42,20 @@ struct InferCeWorker
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// Maps output signal bits to their driver cells
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dict<SigBit, Cell*> sig_to_driver;
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// Maps cell input pins to their source signals
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// Maps cell input pins to their source signals
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dict<SigBit, pool<Cell*>> sig_to_sinks;
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// SAT solver and generator - created once per module
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ezSatPtr ez;
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SatGen satgen;
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// Pre-computed list of combinational cells (for SAT import)
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std::vector<Cell*> comb_cells;
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// Statistics
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int accepted_count = 0;
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int rejected_sat_count = 0;
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int sat_solves = 0;
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InferCeWorker(Module *module, int max_cover, int min_regs)
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: module(module), sigmap(module),
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max_cover(max_cover), min_regs(min_regs),
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ez(), satgen(ez.get(), &sigmap)
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max_cover(max_cover), min_regs(min_regs)
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{
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// Build driver and sink maps
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for (auto cell : module->cells()) {
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@ -139,15 +71,15 @@ struct InferCeWorker
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sig_to_sinks[bit].insert(cell);
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}
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}
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}
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// Import all cells once - circuit constraints are permanent
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for (auto cell : module->cells())
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// Collect combinational cells for SAT
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if (!cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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satgen.importCell(cell);
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_))) {
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comb_cells.push_back(cell);
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}
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}
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}
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// Get downstream signals from a register (BFS forward through combinational logic)
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@ -156,41 +88,32 @@ struct InferCeWorker
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pool<SigBit> visited;
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std::queue<SigBit> worklist;
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// Start from register output Q
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FfData ff(nullptr, reg);
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for (auto bit : sigmap(ff.sig_q)) {
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for (auto bit : sigmap(ff.sig_q))
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if (bit.wire) {
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worklist.push(bit);
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visited.insert(bit);
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}
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}
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while (!worklist.empty() && (int)visited.size() < limit) {
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SigBit bit = worklist.front();
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worklist.pop();
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// Find cells driven by this signal
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for (auto sink_cell : sig_to_sinks[bit]) {
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// Skip registers - don't traverse through them
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if (sink_cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_)))
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continue;
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// Add outputs of this cell to worklist
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for (auto &conn : sink_cell->connections()) {
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if (sink_cell->output(conn.first)) {
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for (auto out_bit : sigmap(conn.second)) {
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for (auto &conn : sink_cell->connections())
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if (sink_cell->output(conn.first))
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for (auto out_bit : sigmap(conn.second))
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if (out_bit.wire && !visited.count(out_bit)) {
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visited.insert(out_bit);
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worklist.push(out_bit);
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}
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}
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}
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}
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}
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}
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return visited;
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}
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@ -209,7 +132,48 @@ struct InferCeWorker
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SigBit bit = worklist.front();
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worklist.pop();
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// Find driver cell
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if (!sig_to_driver.count(bit))
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continue;
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Cell *driver = sig_to_driver[bit];
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if (driver->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_)))
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continue;
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for (auto &conn : driver->connections())
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if (driver->input(conn.first))
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for (auto in_bit : sigmap(conn.second))
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if (in_bit.wire && !visited.count(in_bit)) {
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visited.insert(in_bit);
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worklist.push(in_bit);
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}
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}
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return visited;
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}
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// Get cells in the transitive fanin cone of given signals (for SAT import)
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// This is much faster than importing ALL cells
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pool<Cell*> getConeOfLogic(SigSpec sig)
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{
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pool<Cell*> cone_cells;
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pool<SigBit> visited;
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std::queue<SigBit> worklist;
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// Start from all bits in sig
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for (auto bit : sigmap(sig)) {
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if (bit.wire && !visited.count(bit)) {
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visited.insert(bit);
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worklist.push(bit);
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}
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}
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// BFS backward through drivers
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while (!worklist.empty()) {
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SigBit bit = worklist.front();
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worklist.pop();
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if (!sig_to_driver.count(bit))
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continue;
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@ -218,9 +182,15 @@ struct InferCeWorker
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// Skip registers
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if (driver->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_)))
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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continue;
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// Add this cell to cone
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if (cone_cells.count(driver))
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continue; // Already processed
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cone_cells.insert(driver);
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// Add inputs of driver to worklist
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for (auto &conn : driver->connections()) {
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if (driver->input(conn.first)) {
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@ -234,18 +204,80 @@ struct InferCeWorker
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}
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}
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return visited;
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return cone_cells;
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}
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// Check if OR/AND of signals forms a valid gating condition using SAT
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// Uses a PRE-CREATED SAT solver (passed in) to avoid recreating for each check
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bool isValidGatingSetWithSolver(ezSatPtr &ez, SatGen &satgen,
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const std::vector<SigBit> &conds,
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SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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if (conds.empty())
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return false;
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sat_solves++;
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std::vector<int> d_vec = satgen.importSigSpec(sig_d);
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std::vector<int> q_vec = satgen.importSigSpec(sig_q);
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// Build OR (for enable) or AND (for disable) of condition signals
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std::vector<int> cond_vars;
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for (auto bit : conds)
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cond_vars.push_back(satgen.importSigSpec(SigSpec(bit))[0]);
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int combined_cond;
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if (as_enable) {
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// Clock enable: OR of signals (any signal high = enable)
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combined_cond = ez->expression(ezSAT::OpOr, cond_vars);
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} else {
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// Clock disable: AND of signals (all signals high = disable)
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combined_cond = ez->expression(ezSAT::OpAnd, cond_vars);
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}
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int d_ne_q = ez->vec_ne(d_vec, q_vec);
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// Safe gating: when gating is active (enable=0 or disable=1), D must equal Q
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int gating_active = as_enable ? ez->NOT(combined_cond) : combined_cond;
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int query = ez->AND(gating_active, d_ne_q);
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std::vector<int> assumptions = {query};
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std::vector<int> dummy_exprs;
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std::vector<bool> dummy_vals;
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bool is_valid = !ez->solve(dummy_exprs, dummy_vals, assumptions);
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if (!is_valid)
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rejected_sat_count++;
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return is_valid;
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}
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// Wrapper that creates a fresh SAT solver (used for standalone checks)
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bool isValidGatingSet(const std::vector<SigBit> &conds, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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if (conds.empty())
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return false;
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pool<Cell*> cone = getConeOfLogic(sig_d);
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ezSatPtr ez;
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SatGen satgen(ez.get(), &sigmap);
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for (auto cell : cone)
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satgen.importCell(cell);
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return isValidGatingSetWithSolver(ez, satgen, conds, sig_d, sig_q, as_enable);
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}
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// Binary search to minimize the gating condition set
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// Tries to remove half of the signals at a time
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void minimizeGatingCondition(
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// Uses pre-created SAT solver to avoid recreating for each check
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void minimizeGatingConditionWithSolver(
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ezSatPtr &ez, SatGen &satgen,
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std::vector<SigBit> &good_conds,
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std::vector<SigBit>::iterator begin,
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std::vector<SigBit>::iterator end,
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SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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int half_len = (end - begin) / 2;
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if (half_len == 0)
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return;
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@ -257,78 +289,90 @@ struct InferCeWorker
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test_conds.insert(test_conds.end(), begin, mid);
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test_conds.insert(test_conds.end(), end, good_conds.end());
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if (!test_conds.empty() && isValidGatingSet(test_conds, sig_d, sig_q, as_enable)) {
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if (!test_conds.empty() && isValidGatingSetWithSolver(ez, satgen, test_conds, sig_d, sig_q, as_enable)) {
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// Can remove [mid, end)
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good_conds.erase(mid, end);
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// Recurse on remaining half
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minimizeGatingCondition(good_conds, begin, begin + half_len, sig_d, sig_q, as_enable);
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minimizeGatingConditionWithSolver(ez, satgen, good_conds, begin, begin + half_len, sig_d, sig_q, as_enable);
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} else {
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// Cannot remove all of [mid, end), try to minimize each half
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if (end - mid > 1)
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minimizeGatingCondition(good_conds, mid, end, sig_d, sig_q, as_enable);
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minimizeGatingCondition(good_conds, begin, mid, sig_d, sig_q, as_enable);
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minimizeGatingConditionWithSolver(ez, satgen, good_conds, mid, end, sig_d, sig_q, as_enable);
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minimizeGatingConditionWithSolver(ez, satgen, good_conds, begin, mid, sig_d, sig_q, as_enable);
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}
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}
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// Wrapper for standalone use (creates fresh solver)
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void minimizeGatingCondition(
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std::vector<SigBit> &good_conds,
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std::vector<SigBit>::iterator begin,
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std::vector<SigBit>::iterator end,
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SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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pool<Cell*> cone = getConeOfLogic(sig_d);
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ezSatPtr ez;
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SatGen satgen(ez.get(), &sigmap);
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for (auto cell : cone)
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satgen.importCell(cell);
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minimizeGatingConditionWithSolver(ez, satgen, good_conds, begin, end, sig_d, sig_q, as_enable);
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}
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// Find gating condition for a register
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// Returns empty vector if no valid condition found
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std::pair<std::vector<SigBit>, bool> findGatingCondition(Cell *reg)
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// Returns: {gating_conds, is_enable, cone_size}
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std::tuple<std::vector<SigBit>, bool, int> findGatingCondition(Cell *reg)
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{
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FfData ff(nullptr, reg);
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// Get candidate signals downstream of this register
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// pool<SigBit> downstream = getDownstreamSignals(reg, max_cover);
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// if (downstream.empty()) {
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// log_debug(" No downstream candidates for %s\n", log_id(reg));
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// return {{}, false};
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// }
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// Also include upstream signals that could affect D
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pool<SigBit> d_inputs;
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for (auto bit : sigmap(ff.sig_d))
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if (bit.wire)
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d_inputs.insert(bit);
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pool<SigBit> upstream = getUpstreamSignals(d_inputs, max_cover);
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// Combine and limit candidates
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std::vector<SigBit> candidates;
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// for (auto bit : downstream)
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// candidates.push_back(bit);
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// for (auto bit : upstream)
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// if (!downstream.count(bit))
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// candidates.push_back(bit);
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for (auto bit : upstream)
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candidates.push_back(bit);
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if ((int)candidates.size() > max_cover)
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candidates.resize(max_cover);
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log_debug(" Found %zu candidate signals\n", candidates.size());
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if (candidates.empty())
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return {{}, false, 0};
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// Try as clock enable first (more common)
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if (isValidGatingSet(candidates, ff.sig_d, ff.sig_q, true)) {
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minimizeGatingCondition(candidates, candidates.begin(), candidates.end(),
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ff.sig_d, ff.sig_q, true);
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if (!candidates.empty()) {
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return {candidates, true}; // true = clock enable
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}
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// Create SAT solver ONCE for this register
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pool<Cell*> cone = getConeOfLogic(ff.sig_d);
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int cone_size = (int)cone.size();
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// Skip registers with trivial cones (not worth gating) or huge cones (too expensive)
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const int MIN_CONE_SIZE = 5;
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const int MAX_CONE_SIZE = 500;
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if (cone_size < MIN_CONE_SIZE || cone_size > MAX_CONE_SIZE)
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return {{}, false, cone_size};
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ezSatPtr ez;
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SatGen satgen(ez.get(), &sigmap);
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for (auto cell : cone)
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satgen.importCell(cell);
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// Try as clock enable first
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if (isValidGatingSetWithSolver(ez, satgen, candidates, ff.sig_d, ff.sig_q, true)) {
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minimizeGatingConditionWithSolver(ez, satgen, candidates, candidates.begin(), candidates.end(),
|
||||
ff.sig_d, ff.sig_q, true);
|
||||
if (!candidates.empty())
|
||||
return {candidates, true, cone_size};
|
||||
}
|
||||
|
||||
// Try as clock disable
|
||||
if (isValidGatingSet(candidates, ff.sig_d, ff.sig_q, false)) {
|
||||
minimizeGatingCondition(candidates, candidates.begin(), candidates.end(),
|
||||
ff.sig_d, ff.sig_q, false);
|
||||
if (!candidates.empty()) {
|
||||
return {candidates, false}; // false = clock disable
|
||||
}
|
||||
if (isValidGatingSetWithSolver(ez, satgen, candidates, ff.sig_d, ff.sig_q, false)) {
|
||||
minimizeGatingConditionWithSolver(ez, satgen, candidates, candidates.begin(), candidates.end(),
|
||||
ff.sig_d, ff.sig_q, false);
|
||||
if (!candidates.empty())
|
||||
return {candidates, false, cone_size};
|
||||
}
|
||||
|
||||
return {{}, false};
|
||||
return {{}, false, cone_size};
|
||||
}
|
||||
|
||||
// Insert clock gating logic for a group of registers
|
||||
|
|
@ -339,9 +383,6 @@ struct InferCeWorker
|
|||
if (regs.empty() || gating_conds.empty())
|
||||
return;
|
||||
|
||||
log(" Inserting clock gate for %zu registers with %zu condition signals\n",
|
||||
regs.size(), gating_conds.size());
|
||||
|
||||
// Build gating condition: OR for enable, AND for disable
|
||||
SigBit gating_signal;
|
||||
if (gating_conds.size() == 1) {
|
||||
|
|
@ -371,7 +412,6 @@ struct InferCeWorker
|
|||
FfData ff(nullptr, reg);
|
||||
|
||||
if (ff.has_ce) {
|
||||
// Already has CE, AND with new condition
|
||||
Wire *combined_ce = module->addWire(NEW_ID);
|
||||
module->addAnd(NEW_ID, ff.sig_ce, gating_signal, combined_ce);
|
||||
ff.sig_ce = combined_ce;
|
||||
|
|
@ -385,8 +425,7 @@ struct InferCeWorker
|
|||
}
|
||||
}
|
||||
|
||||
// Check if register can be added to an existing gate (subset/superset matching)
|
||||
// Returns true if the existing gate's condition is a valid gating condition for this register
|
||||
// Check if register can be added to an existing gate
|
||||
bool canReuseGate(const std::vector<SigBit> &existing_conds, Cell *reg, bool is_enable)
|
||||
{
|
||||
FfData ff(nullptr, reg);
|
||||
|
|
@ -396,9 +435,6 @@ struct InferCeWorker
|
|||
// Main processing function
|
||||
void run()
|
||||
{
|
||||
log("Processing module %s\n", log_id(module));
|
||||
|
||||
// Collect all registers
|
||||
std::vector<Cell*> registers;
|
||||
for (auto cell : module->cells()) {
|
||||
if (!cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
|
||||
|
|
@ -408,116 +444,87 @@ struct InferCeWorker
|
|||
continue;
|
||||
|
||||
FfData ff(nullptr, cell);
|
||||
|
||||
// Skip registers that already have CE
|
||||
if (ff.has_ce) {
|
||||
log_debug(" Skipping %s: already has CE\n", log_id(cell));
|
||||
if (ff.has_ce || !ff.has_clk)
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!ff.has_clk) {
|
||||
log_debug(" Skipping %s: no clock\n", log_id(cell));
|
||||
continue;
|
||||
}
|
||||
|
||||
registers.push_back(cell);
|
||||
}
|
||||
|
||||
log(" Found %zu registers without CE\n", registers.size());
|
||||
log("Processing module %s: %zu cells, %zu flip-flops, %zu wires\n",
|
||||
log_id(module), module->cells().size(), registers.size(), module->wires().size());
|
||||
|
||||
if (registers.empty())
|
||||
return;
|
||||
|
||||
// Inverted index approach: net -> list of gate indices containing that net
|
||||
// This allows finding subsets/supersets, not just exact matches
|
||||
struct AcceptedGate {
|
||||
std::vector<SigBit> conds;
|
||||
pool<SigBit> cond_set; // For fast subset/superset checks
|
||||
pool<SigBit> cond_set;
|
||||
std::vector<Cell*> regs;
|
||||
bool is_enable;
|
||||
};
|
||||
std::vector<AcceptedGate> accepted_gates;
|
||||
dict<SigBit, std::vector<size_t>> net_to_accepted; // Inverted index
|
||||
dict<SigBit, std::vector<size_t>> net_to_accepted;
|
||||
|
||||
int processed = 0;
|
||||
int reg_idx = 0;
|
||||
for (auto reg : registers) {
|
||||
if (processed % 100 == 0 && processed > 0)
|
||||
log(" Processed %d/%zu registers\n", processed, registers.size());
|
||||
processed++;
|
||||
auto [gating_conds, is_enable, cone_size] = findGatingCondition(reg);
|
||||
log("Processing register %d/%zu: %s (cone=%d)\n", ++reg_idx, registers.size(), log_id(reg), cone_size);
|
||||
|
||||
log_debug("Processing register %s\n", log_id(reg));
|
||||
|
||||
auto [gating_conds, is_enable] = findGatingCondition(reg);
|
||||
|
||||
if (gating_conds.empty()) {
|
||||
log_debug(" No valid gating condition found\n");
|
||||
if (gating_conds.empty())
|
||||
continue;
|
||||
}
|
||||
|
||||
// Build set of condition signals for this register
|
||||
pool<SigBit> cond_set;
|
||||
for (auto bit : gating_conds)
|
||||
cond_set.insert(bit);
|
||||
|
||||
// Find all accepted gates sharing any net with this register's condition
|
||||
// Find candidate gates sharing any net
|
||||
pool<size_t> candidate_gates;
|
||||
for (auto bit : gating_conds) {
|
||||
if (net_to_accepted.count(bit)) {
|
||||
for (auto bit : gating_conds)
|
||||
if (net_to_accepted.count(bit))
|
||||
for (auto idx : net_to_accepted[bit])
|
||||
candidate_gates.insert(idx);
|
||||
}
|
||||
}
|
||||
|
||||
// Try to find a compatible existing gate (SAT-verify each candidate)
|
||||
// HEURISTIC: Only check top 3 gates (by size) for reuse
|
||||
const int MAX_REUSE_CHECKS = 3;
|
||||
|
||||
std::vector<size_t> sorted_candidates(candidate_gates.begin(), candidate_gates.end());
|
||||
std::sort(sorted_candidates.begin(), sorted_candidates.end(), [&](size_t a, size_t b) {
|
||||
return accepted_gates[a].regs.size() > accepted_gates[b].regs.size();
|
||||
});
|
||||
|
||||
bool found_match = false;
|
||||
for (auto idx : candidate_gates) {
|
||||
auto &gate = accepted_gates[idx];
|
||||
int checked = 0;
|
||||
for (auto idx : sorted_candidates) {
|
||||
if (checked >= MAX_REUSE_CHECKS)
|
||||
break;
|
||||
|
||||
// Must match enable/disable polarity
|
||||
auto &gate = accepted_gates[idx];
|
||||
if (gate.is_enable != is_enable)
|
||||
continue;
|
||||
|
||||
// Check if existing gate's condition works for this register
|
||||
// This allows: gate condition {x,y} can work for register with {x,y,z}
|
||||
// (existing is subset) or register with {x} (existing is superset)
|
||||
checked++;
|
||||
if (canReuseGate(gate.conds, reg, is_enable)) {
|
||||
gate.regs.push_back(reg);
|
||||
log_debug(" Reusing existing gate %zu for %s (flexible match)\n",
|
||||
idx, log_id(reg));
|
||||
found_match = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!found_match) {
|
||||
// Create new accepted gate
|
||||
size_t new_idx = accepted_gates.size();
|
||||
accepted_gates.push_back({gating_conds, cond_set, {reg}, is_enable});
|
||||
|
||||
// Update inverted index
|
||||
for (auto bit : gating_conds)
|
||||
net_to_accepted[bit].push_back(new_idx);
|
||||
|
||||
log(" Found new gating condition for %s (%s)\n",
|
||||
log_id(reg), is_enable ? "enable" : "disable");
|
||||
}
|
||||
}
|
||||
|
||||
// Insert clock gates for groups that meet minimum register threshold
|
||||
int gates_inserted = 0;
|
||||
// Insert clock gates for groups meeting threshold
|
||||
for (auto &gate : accepted_gates) {
|
||||
if ((int)gate.regs.size() >= min_regs) {
|
||||
insertClockGate(gate.regs, gate.conds, gate.is_enable);
|
||||
gates_inserted++;
|
||||
accepted_count += gate.regs.size();
|
||||
} else {
|
||||
log_debug(" Skipping gating condition (only %zu registers, need %d)\n",
|
||||
gate.regs.size(), min_regs);
|
||||
}
|
||||
}
|
||||
|
||||
log(" Inserted %d clock gates\n", gates_inserted);
|
||||
log(" Statistics: accepted=%d, rejected_sat=%d\n",
|
||||
accepted_count, rejected_sat_count);
|
||||
log(" SAT stats: literals=%d, expressions=%d\n",
|
||||
ez->numLiterals(), ez->numExpressions());
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -568,29 +575,14 @@ struct InferCePass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
log("Configuration: max_cover=%d, min_regs=%d\n", max_cover, min_regs);
|
||||
|
||||
// Clear profile file and write header
|
||||
std::ofstream clear_file("ff_profile.txt", std::ios::trunc);
|
||||
clear_file << "Flip-Flop Profile Report\n";
|
||||
clear_file << "========================\n";
|
||||
clear_file.close();
|
||||
|
||||
int total_gates = 0;
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
// Profile BEFORE clock gating
|
||||
profileFlipFlops(module, "ff_profile.txt", "BEFORE infer_ce");
|
||||
|
||||
InferCeWorker worker(module, max_cover, min_regs);
|
||||
worker.run();
|
||||
total_gates += worker.accepted_count;
|
||||
|
||||
// Profile AFTER clock gating
|
||||
profileFlipFlops(module, "ff_profile.txt", "AFTER infer_ce");
|
||||
}
|
||||
|
||||
log("Total clock gates inserted: %d\n", total_gates);
|
||||
log("Inserted clock enables for %d registers.\n", total_gates);
|
||||
}
|
||||
} InferCePass;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue