mirror of https://github.com/YosysHQ/yosys.git
Added initial impl based on OpenROAD
This commit is contained in:
AdvaySingh1
parent
d7277fcb3a
commit
feffbbe32c
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@ -14,346 +14,535 @@
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ff.h"
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#include "kernel/satgen.h"
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#include <fstream>
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#include <queue>
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#include <algorithm>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Maximum depth for BFS exploration of input cone
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static const int MAX_INPUT_DEPTH = 10;
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// If true, exclude Q (feedback) bits from enable input set
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static const bool EXCLUDE_Q_FROM_ENABLE = true;
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// Configuration
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static const int DEFAULT_MAX_COVER = 100; // Max candidate signals to consider
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static const int DEFAULT_MIN_REGS = 1; // Min registers per clock gate
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static const int DEFAULT_SIM_ITERATIONS = 10; // Random simulation iterations for pruning
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struct SatClockgateWorker
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{
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Module *module;
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SigMap sigmap;
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// Configuration
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int max_cover;
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int min_regs;
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int sim_iterations;
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// Maps output signal bits to their driver cells
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dict<SigBit, Cell*> sig_to_driver;
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// Q bits to exclude from enable input set (set per-FF)
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pool<SigBit> q_bits;
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// Maps cell input pins to their source signals
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dict<SigBit, pool<Cell*>> sig_to_sinks;
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// SAT solver and generator - created once per module
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ezSatPtr ez;
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SatGen satgen;
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SatClockgateWorker(Module *module) : module(module), sigmap(module), ez(), satgen(ez.get(), &sigmap)
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// Statistics
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int accepted_count = 0;
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int rejected_sim_count = 0;
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int rejected_sat_count = 0;
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SatClockgateWorker(Module *module, int max_cover, int min_regs, int sim_iterations)
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: module(module), sigmap(module),
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max_cover(max_cover), min_regs(min_regs), sim_iterations(sim_iterations),
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ez(), satgen(ez.get(), &sigmap)
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{
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// Build driver map: for each signal bit, find which cell drives it
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// Build driver and sink maps
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections()) {
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if (cell->output(conn.first)) {
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for (auto bit : sigmap(conn.second))
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sig_to_driver[bit] = cell;
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if (bit.wire)
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sig_to_driver[bit] = cell;
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}
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if (cell->input(conn.first)) {
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for (auto bit : sigmap(conn.second))
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if (bit.wire)
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sig_to_sinks[bit].insert(cell);
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}
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}
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}
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// Import all cells once - circuit constraints are permanent
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for (auto cell : module->cells())
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satgen.importCell(cell);
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if (!cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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satgen.importCell(cell);
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}
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// Set Q bits to exclude for current FF
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void set_excluded_q_bits(SigSpec sig_q)
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// Get downstream signals from a register (BFS forward through combinational logic)
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pool<SigBit> getDownstreamSignals(Cell *reg, int limit)
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{
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q_bits.clear();
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if (EXCLUDE_Q_FROM_ENABLE) {
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for (auto bit : sigmap(sig_q))
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q_bits.insert(bit);
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pool<SigBit> result;
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pool<SigBit> visited;
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std::queue<SigBit> worklist;
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// Start from register output Q
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FfData ff(nullptr, reg);
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for (auto bit : sigmap(ff.sig_q)) {
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if (bit.wire) {
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worklist.push(bit);
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visited.insert(bit);
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}
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}
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}
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// Get the set of input signals feeding into a given signal (one level back)
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pool<SigBit> get_input_signals(SigBit bit)
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{
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pool<SigBit> inputs;
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bit = sigmap(bit);
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if (!sig_to_driver.count(bit))
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return inputs; // Primary input or constant
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Cell *driver = sig_to_driver[bit];
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for (auto &conn : driver->connections()) {
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if (driver->input(conn.first)) {
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for (auto input_bit : sigmap(conn.second)) {
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if (input_bit.wire != nullptr && !q_bits.count(input_bit))
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inputs.insert(input_bit);
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while (!worklist.empty() && (int)result.size() < limit) {
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SigBit bit = worklist.front();
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worklist.pop();
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result.insert(bit);
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// Find cells driven by this signal
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for (auto sink_cell : sig_to_sinks[bit]) {
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// Skip registers - don't traverse through them
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if (sink_cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_)))
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continue;
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// Add outputs of this cell to worklist
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for (auto &conn : sink_cell->connections()) {
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if (sink_cell->output(conn.first)) {
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for (auto out_bit : sigmap(conn.second)) {
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if (out_bit.wire && !visited.count(out_bit)) {
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visited.insert(out_bit);
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worklist.push(out_bit);
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}
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}
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}
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}
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}
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}
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return inputs;
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return result;
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}
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// Check if OR(input_set) is exactly equivalent to (D != Q)
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// Returns true if COI ↔ (D≠Q) for all circuit states (exact clock gating)
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// TODO: Consider pruning the expressions list — expressions accumulate across
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// calls (OR, XOR, NE per query). For large designs with many FFs, this
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// could cause memory growth. Options: solver checkpoints, fresh solver
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// per FF with COI-only cell import, or periodic expression cleanup.
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bool input_set_is_enable(const pool<SigBit> &input_set, SigSpec sig_d, SigSpec sig_q)
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// Get upstream signals feeding into given signals (BFS backward)
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pool<SigBit> getUpstreamSignals(const pool<SigBit> &start_signals, int limit)
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{
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if (input_set.empty())
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pool<SigBit> result;
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pool<SigBit> visited;
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std::queue<SigBit> worklist;
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for (auto bit : start_signals) {
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worklist.push(bit);
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visited.insert(bit);
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}
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while (!worklist.empty() && (int)result.size() < limit) {
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SigBit bit = worklist.front();
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worklist.pop();
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result.insert(bit);
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// Find driver cell
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if (!sig_to_driver.count(bit))
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continue;
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Cell *driver = sig_to_driver[bit];
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// Skip registers
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if (driver->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_)))
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continue;
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// Add inputs of driver to worklist
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for (auto &conn : driver->connections()) {
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if (driver->input(conn.first)) {
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for (auto in_bit : sigmap(conn.second)) {
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if (in_bit.wire && !visited.count(in_bit)) {
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visited.insert(in_bit);
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worklist.push(in_bit);
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}
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}
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}
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}
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}
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return result;
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}
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// Check if a candidate signal is a valid gating condition using SAT
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// Safe gating check: sig=1 → D==Q (i.e., (sig ∧ (D≠Q)) is UNSAT)
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bool isValidGatingSignal(SigBit candidate, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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std::vector<int> d_vec = satgen.importSigSpec(sig_d);
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std::vector<int> q_vec = satgen.importSigSpec(sig_q);
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int cand_var = satgen.importSigSpec(SigSpec(candidate))[0];
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// D != Q
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int d_ne_q = ez->vec_ne(d_vec, q_vec);
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// For clock enable (active high): when enable=0, D must equal Q
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// Check: (!enable ∧ (D≠Q)) is UNSAT
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// For clock disable (active low): when disable=1, D must equal Q
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// Check: (disable ∧ (D≠Q)) is UNSAT
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int gating_active = as_enable ? ez->NOT(cand_var) : cand_var;
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int query = ez->AND(gating_active, d_ne_q);
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std::vector<int> assumptions = {query};
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std::vector<int> dummy_exprs;
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std::vector<bool> dummy_vals;
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return !ez->solve(dummy_exprs, dummy_vals, assumptions);
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}
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// Simple random simulation test to quickly prune candidates
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bool simulationTest(SigBit candidate, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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// For now, skip simulation and go straight to SAT
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// TODO: Implement random simulation for faster pruning
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return true;
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}
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// Binary search to minimize the gating condition set
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// Tries to remove half of the signals at a time
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void minimizeGatingCondition(
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std::vector<SigBit> &good_conds,
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std::vector<SigBit>::iterator begin,
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std::vector<SigBit>::iterator end,
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SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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int half_len = (end - begin) / 2;
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if (half_len == 0)
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return;
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auto mid = begin + half_len;
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// Try removing [mid, end) from the condition
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std::vector<SigBit> test_conds;
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test_conds.insert(test_conds.end(), good_conds.begin(), begin);
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test_conds.insert(test_conds.end(), begin, mid);
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test_conds.insert(test_conds.end(), end, good_conds.end());
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if (!test_conds.empty() && isValidGatingSet(test_conds, sig_d, sig_q, as_enable)) {
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// Can remove [mid, end)
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good_conds.erase(mid, end);
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// Recurse on remaining half
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minimizeGatingCondition(good_conds, begin, begin + half_len, sig_d, sig_q, as_enable);
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} else {
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// Cannot remove all of [mid, end), try to minimize each half
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if (end - mid > 1)
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minimizeGatingCondition(good_conds, mid, end, sig_d, sig_q, as_enable);
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minimizeGatingCondition(good_conds, begin, mid, sig_d, sig_q, as_enable);
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}
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}
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// Check if OR/AND of signals forms a valid gating condition
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bool isValidGatingSet(const std::vector<SigBit> &conds, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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if (conds.empty())
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return false;
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// Import D and Q (uses cached literals if already imported)
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std::vector<int> d_vec = satgen.importSigSpec(sig_d);
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std::vector<int> q_vec = satgen.importSigSpec(sig_q);
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// Build COI = OR(input_set)
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std::vector<int> input_vars;
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for (auto bit : input_set)
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input_vars.push_back(satgen.importSigSpec(SigSpec(bit))[0]);
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int coi = ez->expression(ezSAT::OpOr, input_vars);
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// Build OR (for enable) or AND (for disable) of condition signals
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std::vector<int> cond_vars;
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for (auto bit : conds)
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cond_vars.push_back(satgen.importSigSpec(SigSpec(bit))[0]);
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int combined_cond;
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if (as_enable) {
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// Clock enable: OR of signals (any signal high = enable)
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combined_cond = ez->expression(ezSAT::OpOr, cond_vars);
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} else {
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// Clock disable: AND of signals (all signals high = disable)
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combined_cond = ez->expression(ezSAT::OpAnd, cond_vars);
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}
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// Build D != Q (single bit: is any bit different?)
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int d_ne_q = ez->vec_ne(d_vec, q_vec);
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// Query: COI XOR (D≠Q) — want this UNSAT (meaning COI ↔ D≠Q)
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// Use solve() with assumption instead of permanent assume()
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int query = ez->XOR(coi, d_ne_q);
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// Safe gating: when gating is active (enable=0 or disable=1), D must equal Q
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int gating_active = as_enable ? ez->NOT(combined_cond) : combined_cond;
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int query = ez->AND(gating_active, d_ne_q);
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std::vector<int> assumptions = {query};
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std::vector<int> dummy_model_exprs;
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std::vector<bool> dummy_model_vals;
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std::vector<int> dummy_exprs;
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std::vector<bool> dummy_vals;
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// If UNSAT: COI is exactly when D≠Q → perfect enable
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return !ez->solve(dummy_model_exprs, dummy_model_vals, assumptions);
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return !ez->solve(dummy_exprs, dummy_vals, assumptions);
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}
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// Recursively determine the enable input set via BFS expansion
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// Seeds initial input set from sig_d, Q bits filtered via get_input_signals
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bool determine_enable_recursive(pool<SigBit> &input_set, SigSpec sig_d, SigSpec sig_q, int depth)
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// Find gating condition for a register
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// Returns empty vector if no valid condition found
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std::pair<std::vector<SigBit>, bool> findGatingCondition(Cell *reg)
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{
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if (depth > MAX_INPUT_DEPTH) {
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log_debug(" Max depth reached, giving up\n");
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return false;
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FfData ff(nullptr, reg);
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// Get candidate signals downstream of this register
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pool<SigBit> downstream = getDownstreamSignals(reg, max_cover);
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if (downstream.empty()) {
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log_debug(" No downstream candidates for %s\n", log_id(reg));
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return {{}, false};
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}
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// Seed initial input set from sig_d on first call
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if (depth == 1 && input_set.empty()) {
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for (auto bit : sigmap(sig_d)) {
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if (bit.wire != nullptr) {
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for (auto input_bit : get_input_signals(bit))
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input_set.insert(input_bit);
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}
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}
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if (input_set.empty()) {
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log_debug(" No inputs to D (besides Q)\n");
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return false;
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}
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log_debug(" Initial input set has %zu signals\n", input_set.size());
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}
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// Check if current input set works as enable
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if (input_set_is_enable(input_set, sig_d, sig_q)) {
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log_debug(" Found enable at depth %d with %zu signals\n", depth, input_set.size());
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return true;
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}
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// Expand input set via BFS (one more level)
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pool<SigBit> new_inputs;
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for (auto bit : input_set) {
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for (auto input_bit : get_input_signals(bit)) {
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if (!input_set.count(input_bit))
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new_inputs.insert(input_bit);
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// Also include upstream signals that could affect D
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pool<SigBit> d_inputs;
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for (auto bit : sigmap(ff.sig_d))
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if (bit.wire)
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d_inputs.insert(bit);
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pool<SigBit> upstream = getUpstreamSignals(d_inputs, max_cover);
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// Combine and limit candidates
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std::vector<SigBit> candidates;
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for (auto bit : downstream)
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candidates.push_back(bit);
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for (auto bit : upstream)
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if (!downstream.count(bit))
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candidates.push_back(bit);
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if ((int)candidates.size() > max_cover)
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candidates.resize(max_cover);
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log_debug(" Found %zu candidate signals\n", candidates.size());
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// Try as clock enable first (more common)
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if (isValidGatingSet(candidates, ff.sig_d, ff.sig_q, true)) {
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minimizeGatingCondition(candidates, candidates.begin(), candidates.end(),
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ff.sig_d, ff.sig_q, true);
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if (!candidates.empty()) {
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accepted_count++;
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return {candidates, true}; // true = clock enable
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}
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}
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if (new_inputs.empty()) {
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log_debug(" No more inputs to explore at depth %d\n", depth);
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return false;
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// Try as clock disable
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if (isValidGatingSet(candidates, ff.sig_d, ff.sig_q, false)) {
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minimizeGatingCondition(candidates, candidates.begin(), candidates.end(),
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ff.sig_d, ff.sig_q, false);
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if (!candidates.empty()) {
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accepted_count++;
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return {candidates, false}; // false = clock disable
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}
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}
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// Add new inputs and recurse
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for (auto bit : new_inputs)
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input_set.insert(bit);
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return determine_enable_recursive(input_set, sig_d, sig_q, depth + 1);
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rejected_sat_count++;
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return {{}, false};
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}
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// Create CE logic based on the input set and modify the FF
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// The enable condition is: when all input_set bits are 0, D == Q (hold)
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// So CE should be: OR of all input_set bits (active high: CE=1 means update)
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void create_ce_logic(const pool<SigBit> &input_set, FfData &ff)
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// Insert clock gating logic for a group of registers
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void insertClockGate(const std::vector<Cell*> ®s,
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const std::vector<SigBit> &gating_conds,
|
||||
bool as_enable)
|
||||
{
|
||||
if (input_set.empty())
|
||||
if (regs.empty() || gating_conds.empty())
|
||||
return;
|
||||
|
||||
log(" Creating CE from %zu input signals\n", input_set.size());
|
||||
|
||||
// Build CE as OR of all input signals
|
||||
// CE = 1 when any input is 1 (meaning: update the register)
|
||||
// CE = 0 when all inputs are 0 (meaning: hold, since D == Q)
|
||||
SigSpec ce_inputs;
|
||||
for (auto bit : input_set)
|
||||
ce_inputs.append(bit);
|
||||
|
||||
SigBit ce_signal;
|
||||
if (GetSize(ce_inputs) == 1) {
|
||||
ce_signal = ce_inputs[0];
|
||||
|
||||
log(" Inserting clock gate for %zu registers with %zu condition signals\n",
|
||||
regs.size(), gating_conds.size());
|
||||
|
||||
// Build gating condition: OR for enable, AND for disable
|
||||
SigBit gating_signal;
|
||||
if (gating_conds.size() == 1) {
|
||||
gating_signal = gating_conds[0];
|
||||
} else {
|
||||
// Create OR gate: CE = |input_set
|
||||
Wire *ce_wire = module->addWire(NEW_ID);
|
||||
module->addReduceOr(NEW_ID, ce_inputs, ce_wire);
|
||||
ce_signal = ce_wire;
|
||||
}
|
||||
|
||||
// Set the CE on the FF
|
||||
ff.has_ce = true;
|
||||
ff.sig_ce = ce_signal;
|
||||
ff.pol_ce = true; // Active high
|
||||
|
||||
log(" CE signal: %s\n", log_signal(ce_signal));
|
||||
}
|
||||
|
||||
// Process a single FF to find and insert CE
|
||||
bool process_ff(Cell *cell)
|
||||
{
|
||||
FfData ff(nullptr, cell);
|
||||
|
||||
// Skip if already has CE, or doesn't have clock/data
|
||||
if (ff.has_ce) {
|
||||
log_debug(" Skipping %s: already has CE\n", log_id(cell));
|
||||
return false;
|
||||
}
|
||||
if (!ff.has_clk) {
|
||||
log_debug(" Skipping %s: no clock\n", log_id(cell));
|
||||
return false;
|
||||
}
|
||||
if (GetSize(ff.sig_d) == 0 || GetSize(ff.sig_q) == 0) {
|
||||
log_debug(" Skipping %s: no D or Q\n", log_id(cell));
|
||||
return false;
|
||||
}
|
||||
|
||||
log("Processing FF: %s\n", log_id(cell));
|
||||
|
||||
// Set Q bits to exclude from enable candidates
|
||||
set_excluded_q_bits(ff.sig_q);
|
||||
|
||||
// Find enable via recursive BFS + SAT validation
|
||||
pool<SigBit> input_set;
|
||||
if (determine_enable_recursive(input_set, ff.sig_d, ff.sig_q, 1)) {
|
||||
create_ce_logic(input_set, ff);
|
||||
SigSpec cond_inputs;
|
||||
for (auto bit : gating_conds)
|
||||
cond_inputs.append(bit);
|
||||
|
||||
// Emit the modified FF
|
||||
ff.emit();
|
||||
return true;
|
||||
Wire *cond_wire = module->addWire(NEW_ID);
|
||||
if (as_enable)
|
||||
module->addReduceOr(NEW_ID, cond_inputs, cond_wire);
|
||||
else
|
||||
module->addReduceAnd(NEW_ID, cond_inputs, cond_wire);
|
||||
gating_signal = cond_wire;
|
||||
}
|
||||
|
||||
log_debug(" Could not find enable for %s\n", log_id(cell));
|
||||
return false;
|
||||
|
||||
// If disable signal, invert to get enable
|
||||
if (!as_enable) {
|
||||
Wire *inv_wire = module->addWire(NEW_ID);
|
||||
module->addNot(NEW_ID, gating_signal, inv_wire);
|
||||
gating_signal = inv_wire;
|
||||
}
|
||||
|
||||
// Add CE to each register
|
||||
for (auto reg : regs) {
|
||||
FfData ff(nullptr, reg);
|
||||
|
||||
if (ff.has_ce) {
|
||||
// Already has CE, AND with new condition
|
||||
Wire *combined_ce = module->addWire(NEW_ID);
|
||||
module->addAnd(NEW_ID, ff.sig_ce, gating_signal, combined_ce);
|
||||
ff.sig_ce = combined_ce;
|
||||
} else {
|
||||
ff.has_ce = true;
|
||||
ff.sig_ce = gating_signal;
|
||||
ff.pol_ce = true;
|
||||
}
|
||||
|
||||
ff.emit();
|
||||
log(" Added CE to %s\n", log_id(reg));
|
||||
}
|
||||
}
|
||||
|
||||
// Main processing function
|
||||
void run()
|
||||
{
|
||||
log("Processing module %s\n", log_id(module));
|
||||
|
||||
// Collect all registers
|
||||
std::vector<Cell*> registers;
|
||||
for (auto cell : module->cells()) {
|
||||
if (!cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
|
||||
ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
|
||||
ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
|
||||
ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
|
||||
continue;
|
||||
|
||||
FfData ff(nullptr, cell);
|
||||
|
||||
// Skip registers that already have CE
|
||||
if (ff.has_ce) {
|
||||
log_debug(" Skipping %s: already has CE\n", log_id(cell));
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!ff.has_clk) {
|
||||
log_debug(" Skipping %s: no clock\n", log_id(cell));
|
||||
continue;
|
||||
}
|
||||
|
||||
registers.push_back(cell);
|
||||
}
|
||||
|
||||
log(" Found %zu registers without CE\n", registers.size());
|
||||
|
||||
// Track accepted gating conditions for reuse
|
||||
// Maps condition signature to (condition signals, registers, is_enable)
|
||||
dict<std::string, std::tuple<std::vector<SigBit>, std::vector<Cell*>, bool>> accepted_gates;
|
||||
|
||||
int processed = 0;
|
||||
for (auto reg : registers) {
|
||||
if (processed % 100 == 0 && processed > 0)
|
||||
log(" Processed %d/%zu registers\n", processed, registers.size());
|
||||
processed++;
|
||||
|
||||
log_debug("Processing register %s\n", log_id(reg));
|
||||
|
||||
auto [gating_conds, is_enable] = findGatingCondition(reg);
|
||||
|
||||
if (gating_conds.empty()) {
|
||||
log_debug(" No valid gating condition found\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
// Create signature for this gating condition
|
||||
std::string sig;
|
||||
for (auto bit : gating_conds)
|
||||
sig += log_signal(bit) + ",";
|
||||
sig += is_enable ? "E" : "D";
|
||||
|
||||
// Check if we already have this condition
|
||||
if (accepted_gates.count(sig)) {
|
||||
auto &[conds, regs, en] = accepted_gates[sig];
|
||||
regs.push_back(reg);
|
||||
log_debug(" Reusing existing gating condition for %s\n", log_id(reg));
|
||||
} else {
|
||||
accepted_gates[sig] = {gating_conds, {reg}, is_enable};
|
||||
log(" Found new gating condition for %s: %s (%s)\n",
|
||||
log_id(reg), sig.c_str(), is_enable ? "enable" : "disable");
|
||||
}
|
||||
}
|
||||
|
||||
// Insert clock gates for groups that meet minimum register threshold
|
||||
int gates_inserted = 0;
|
||||
for (auto &[sig, data] : accepted_gates) {
|
||||
auto &[conds, regs, is_enable] = data;
|
||||
|
||||
if ((int)regs.size() >= min_regs) {
|
||||
insertClockGate(regs, conds, is_enable);
|
||||
gates_inserted++;
|
||||
} else {
|
||||
log_debug(" Skipping gating condition (only %zu registers, need %d)\n",
|
||||
regs.size(), min_regs);
|
||||
}
|
||||
}
|
||||
|
||||
log(" Inserted %d clock gates\n", gates_inserted);
|
||||
log(" Statistics: accepted=%d, rejected_sat=%d\n",
|
||||
accepted_count, rejected_sat_count);
|
||||
}
|
||||
};
|
||||
|
||||
void dump_flipflops_to_file(RTLIL::Design *design, const std::string &filename)
|
||||
{
|
||||
std::ofstream outfile(filename);
|
||||
if (!outfile.is_open()) {
|
||||
log_error("Cannot open file %s for writing\n", filename.c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
outfile << "Module: " << log_id(module) << "\n";
|
||||
log("Module: %s\n", log_id(module));
|
||||
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->is_builtin_ff()) {
|
||||
outfile << " FF: " << log_id(cell) << " (type: " << log_id(cell->type) << ")\n";
|
||||
log(" FF: %s (type: %s)\n", log_id(cell), log_id(cell->type));
|
||||
}
|
||||
}
|
||||
outfile << "\n";
|
||||
}
|
||||
|
||||
outfile.close();
|
||||
log("Wrote flip-flop list to %s\n", filename.c_str());
|
||||
}
|
||||
|
||||
struct SatClockgatePass : public Pass {
|
||||
SatClockgatePass() : Pass("sat_clockgate", "SAT-based inferred clock gating") { }
|
||||
|
||||
SatClockgatePass() : Pass("sat_clockgate", "SAT-based automatic clock gating") { }
|
||||
|
||||
void help() override
|
||||
{
|
||||
log("\n");
|
||||
log(" sat_clockgate [options] [selection]\n");
|
||||
log("\n");
|
||||
log("This command performs SAT-based inferred clock gating insertion.\n");
|
||||
log("It analyzes flip-flops without explicit clock enables and uses SAT\n");
|
||||
log("to find input conditions under which D == Q (register holds value).\n");
|
||||
log("These conditions become the inferred clock enable.\n");
|
||||
log("This command performs SAT-based automatic clock gating insertion.\n");
|
||||
log("It analyzes registers and uses SAT solving to find signals that can\n");
|
||||
log("serve as clock enable conditions (when the signal is low, D==Q).\n");
|
||||
log("\n");
|
||||
log(" -threshold <n>\n");
|
||||
log(" minimum number of FFs that must share an enable for clock gating\n");
|
||||
log(" to be inserted (default: 1)\n");
|
||||
log("Algorithm based on:\n");
|
||||
log(" - \"Automatic Synthesis of Clock Gating Logic\" by Aaron P. Hurst\n");
|
||||
log(" - OpenROAD's cgt module implementation\n");
|
||||
log("\n");
|
||||
log(" -max_cover <n>\n");
|
||||
log(" maximum number of candidate signals to consider per register\n");
|
||||
log(" (default: %d)\n", DEFAULT_MAX_COVER);
|
||||
log("\n");
|
||||
log(" -min_regs <n>\n");
|
||||
log(" minimum number of registers that must share a gating condition\n");
|
||||
log(" for a clock gate to be inserted (default: %d)\n", DEFAULT_MIN_REGS);
|
||||
log("\n");
|
||||
}
|
||||
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing SAT_CLOCKGATE pass (SAT-based inferred clock gating).\n");
|
||||
|
||||
int threshold = 1;
|
||||
|
||||
log_header(design, "Executing SAT_CLOCKGATE pass.\n");
|
||||
|
||||
int max_cover = DEFAULT_MAX_COVER;
|
||||
int min_regs = DEFAULT_MIN_REGS;
|
||||
int sim_iterations = DEFAULT_SIM_ITERATIONS;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-threshold" && argidx+1 < args.size()) {
|
||||
threshold = std::stoi(args[++argidx]);
|
||||
if (args[argidx] == "-max_cover" && argidx+1 < args.size()) {
|
||||
max_cover = std::stoi(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-min_regs" && argidx+1 < args.size()) {
|
||||
min_regs = std::stoi(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
log("Using threshold: %d\n", threshold);
|
||||
|
||||
// Dump all flip-flops to file (debug)
|
||||
dump_flipflops_to_file(design, "flip_flops.txt");
|
||||
|
||||
int total_converted = 0;
|
||||
|
||||
|
||||
log("Configuration: max_cover=%d, min_regs=%d\n", max_cover, min_regs);
|
||||
|
||||
int total_gates = 0;
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
log("Processing module %s...\n", log_id(module));
|
||||
|
||||
SatClockgateWorker worker(module);
|
||||
|
||||
// Collect FFs to process (can't modify while iterating)
|
||||
std::vector<Cell*> ffs_to_process;
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->is_builtin_ff())
|
||||
ffs_to_process.push_back(cell);
|
||||
}
|
||||
|
||||
int converted = 0;
|
||||
for (auto cell : ffs_to_process) {
|
||||
if (worker.process_ff(cell))
|
||||
converted++;
|
||||
}
|
||||
|
||||
if (converted > 0) {
|
||||
log("Converted %d FFs in module %s\n", converted, log_id(module));
|
||||
total_converted += converted;
|
||||
}
|
||||
SatClockgateWorker worker(module, max_cover, min_regs, sim_iterations);
|
||||
worker.run();
|
||||
total_gates += worker.accepted_count;
|
||||
}
|
||||
|
||||
log("Total FFs with inferred CE: %d\n", total_converted);
|
||||
|
||||
// TODO: Call clockgate pass to convert CEs to ICG cells
|
||||
// if (total_converted >= threshold) {
|
||||
// Pass::call(design, "clockgate");
|
||||
// }
|
||||
|
||||
log("Total clock gates inserted: %d\n", total_gates);
|
||||
}
|
||||
} SatClockgatePass;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue