mirror of https://github.com/YosysHQ/yosys.git
Added passing on the args into the clockgate pass so there's an icg cell for the mapping
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@ -582,6 +582,7 @@ struct SatClockgatePass : public Pass {
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int max_cover = DEFAULT_MAX_COVER;
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int min_regs = DEFAULT_MIN_REGS;
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int sim_iterations = DEFAULT_SIM_ITERATIONS;
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std::vector<std::string> clockgate_args;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -593,9 +594,14 @@ struct SatClockgatePass : public Pass {
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min_regs = std::stoi(args[++argidx]);
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continue;
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}
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break;
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// Pass remaining args to clockgate
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if (args[argidx][0] == '-') {
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clockgate_args.push_back(args[argidx]);
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continue;
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}
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// Non-flag argument (value for previous flag)
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clockgate_args.push_back(args[argidx]);
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}
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extra_args(args, argidx, design);
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log("Configuration: max_cover=%d, min_regs=%d\n", max_cover, min_regs);
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@ -622,7 +628,10 @@ struct SatClockgatePass : public Pass {
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log("Total clock gates inserted: %d\n", total_gates);
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// Convert CEs to actual clock gate cells
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Pass::call(design, "clockgate");
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std::string clockgate_cmd = "clockgate";
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for (auto &arg : clockgate_args)
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clockgate_cmd += " " + arg;
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Pass::call(design, clockgate_cmd);
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}
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} SatClockgatePass;
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