mirror of https://github.com/YosysHQ/yosys.git
Add negopt pass with comprehensive pattern matching
This commit introduces the negopt pass with pre/post optimization modes for handling negation patterns in arithmetic circuits. Pre-optimization patterns (expose for tree balancing): - manual2sub: (a + ~b) + 1 → a - b - sub2neg: a - b → a + (-b) - negexpand: -(a + b) → (-a) + (-b) [with output width fix] - negneg: -(-a) → a - negmux: -(s ? a : b) → s ? (-a) : (-b) Post-optimization patterns (cleanup/rebuild): - negrebuild: (-a) + (-b) → -(a + b) - muxneg: s ? (-a) : (-b) → -(s ? a : b) - neg2sub: a + (-b) → a - b All patterns use nusers() for fanout checking (standard Yosys style). Comprehensive test coverage with positive/negative cases and formal verification via equiv_opt.
This commit is contained in:
tondapusili
parent
7c70026610
commit
643427d9c9
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@ -33,3 +33,20 @@ PEEPOPT_PATTERN += passes/silimate/peepopt_muxinvprop.pmg
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passes/silimate/peepopt_muxmode.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
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OBJS += passes/silimate/negopt.o
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GENFILES += passes/silimate/peepopt_negopt.h
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passes/silimate/negopt.o: passes/silimate/peepopt_negopt.h
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$(eval $(call add_extra_objs,passes/silimate/peepopt_negopt.h))
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PEEPOPT_PATTERN = passes/silimate/peepopt_manual2sub.pmg
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PEEPOPT_PATTERN += passes/silimate/peepopt_sub2neg.pmg
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PEEPOPT_PATTERN += passes/silimate/peepopt_negexpand.pmg
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PEEPOPT_PATTERN += passes/silimate/peepopt_negneg.pmg
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PEEPOPT_PATTERN += passes/silimate/peepopt_negmux.pmg
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PEEPOPT_PATTERN += passes/silimate/peepopt_negrebuild.pmg
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PEEPOPT_PATTERN += passes/silimate/peepopt_muxneg.pmg
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PEEPOPT_PATTERN += passes/silimate/peepopt_neg2sub.pmg
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passes/silimate/peepopt_negopt.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
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@ -0,0 +1,119 @@
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/*
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* Copyright (C) 2025 Silimate, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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//
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// Authored by Abhinav Tondapu of Silimate, Inc.
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//
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool did_something;
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#include "passes/silimate/peepopt_negopt.h"
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struct NegoptPass : public Pass {
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NegoptPass() : Pass("negopt", "optimize negation patterns in arithmetic") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" negopt [options] [selection]\n");
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log("\n");
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log("This pass optimizes negation patterns in arithmetic expressions.\n");
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log("\n");
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log(" -pre\n");
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log(" Run pre-optimization transformations:\n" );
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log(" - manual2sub: a + ~b + 1 => a - b\n" );
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log(" - sub2neg: a - b => a + (-b)\n" );
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log(" - negexpand: -(a + b) => (-a) + (-b)\n");
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log(" - negneg: -(-a) => a\n" );
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log(" - negmux: -(s?a:b) => s?(-a):(-b)\n");
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log("\n");
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log(" -post\n");
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log(" Run post-optimization transformations:\n" );
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log(" - negrebuild: (-a)+(-b) => -(a + b)\n");
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log(" - muxneg: s?(-a):(-b) => -(s?a:b)\n");
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log(" - neg2sub: a + (-b) => a - b\n" );
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log("\n");
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log("When called without options, both -pre and -post are executed.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool run_pre = false;
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bool run_post = false;
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log_header(design, "Executing NEGOPT pass (optimize negation patterns).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-pre") {
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run_pre = true;
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continue;
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}
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if (args[argidx] == "-post") {
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run_post = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!run_pre && !run_post) {
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run_pre = true;
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run_post = true;
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}
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for (auto module : design->selected_modules()) {
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if (run_pre) {
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did_something = true;
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while (did_something) {
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did_something = false;
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peepopt_pm pm(module);
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pm.setup(module->selected_cells());
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pm.run_manual2sub(); // Reduce manual 2's complement to subtraction first
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pm.run_sub2neg();
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pm.run_negexpand();
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pm.run_negneg();
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pm.run_negmux();
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}
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}
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if (run_post) {
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did_something = true;
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while (did_something) {
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did_something = false;
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peepopt_pm pm(module);
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pm.setup(module->selected_cells());
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pm.run_negrebuild();
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pm.run_muxneg();
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pm.run_neg2sub();
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}
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}
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}
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}
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} NegoptPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,171 @@
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pattern manual2sub
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//
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// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
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//
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// Canonicalize manual 2's complement subtraction:
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// Case A: (a + ~b) + 1 ===> a - b
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// Case B: a + (~b + 1) ===> a - b
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//
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// Note: Fanout checking includes module connections to avoid breaking
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// designs where intermediate results are used by output assignments.
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//
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state <SigSpec> minuend subtrahend result_sig
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state <bool> is_signed
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state <SigSpec> inner_y
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// 1. Match the "root" add (the one that produces the final result)
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match root_add
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select root_add->type == $add
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set result_sig port(root_add, \Y)
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set is_signed root_add->getParam(ID::A_SIGNED).as_bool()
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endmatch
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// 2. Case A: (a + ~b) + 1
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// Check if root_add has a constant 1
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code root_add inner_y
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{
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SigSpec pa = root_add->getPort(ID::A);
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SigSpec pb = root_add->getPort(ID::B);
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auto is_one = [](SigSpec s) {
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if (!s.is_fully_const()) return false;
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Const c = s.as_const();
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for (int i = 0; i < c.size(); i++) {
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if (i == 0 && c[i] != State::S1) return false;
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if (i > 0 && c[i] != State::S0) return false;
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}
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return true;
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};
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if (is_one(pa)) {
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inner_y = pb;
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} else if (is_one(pb)) {
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inner_y = pa;
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} else {
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branch;
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reject;
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}
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}
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endcode
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// Find the inner add
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match inner_add_A
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select inner_add_A->type == $add
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index <SigSpec> port(inner_add_A, \Y) === inner_y
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select nusers(port(inner_add_A, \Y)) == 2
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endmatch
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// Find the NOT gate on one of the ports of inner_add_A
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match not_gate_A
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select not_gate_A->type == $not
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filter not_gate_A->getPort(ID::Y) == inner_add_A->getPort(ID::A) || not_gate_A->getPort(ID::Y) == inner_add_A->getPort(ID::B)
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set subtrahend port(not_gate_A, \A)
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endmatch
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code root_add inner_add_A not_gate_A subtrahend minuend result_sig is_signed
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{
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// Require consistent signedness on the root add.
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if (root_add->getParam(ID::B_SIGNED).as_bool() != is_signed)
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reject;
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if (inner_add_A->getParam(ID::A_SIGNED).as_bool() != is_signed)
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reject;
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if (inner_add_A->getParam(ID::B_SIGNED).as_bool() != is_signed)
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reject;
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if (not_gate_A->getPort(ID::Y) == inner_add_A->getPort(ID::A))
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minuend = inner_add_A->getPort(ID::B);
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else
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minuend = inner_add_A->getPort(ID::A);
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// Create the subtraction cell
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log("manual2sub in %s: Found (a + ~b) + 1 pattern, creating $sub for %s\n", log_id(module), log_signal(result_sig));
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Cell *sub = module->addSub(NEW_ID, minuend, subtrahend, result_sig, is_signed);
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// Let fixup_parameters handle width adjustments
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sub->fixup_parameters();
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// Remove old cells
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autoremove(root_add);
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autoremove(inner_add_A);
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autoremove(not_gate_A);
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did_something = true;
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accept;
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}
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endcode
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// 3. Case B: a + (~b + 1)
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code root_add
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// Just fall through to the next match
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endcode
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// Find the inner add on either port of root_add
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match inner_add_B
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select inner_add_B->type == $add
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filter inner_add_B->getPort(ID::Y) == root_add->getPort(ID::A) || inner_add_B->getPort(ID::Y) == root_add->getPort(ID::B)
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select nusers(port(inner_add_B, \Y)) == 2
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endmatch
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// Check if inner_add_B has a constant 1 and a NOT gate
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match not_gate_B
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select not_gate_B->type == $not
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filter not_gate_B->getPort(ID::Y) == inner_add_B->getPort(ID::A) || not_gate_B->getPort(ID::Y) == inner_add_B->getPort(ID::B)
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endmatch
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code root_add inner_add_B not_gate_B minuend subtrahend result_sig is_signed
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{
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// Require consistent signedness on the root add.
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if (root_add->getParam(ID::B_SIGNED).as_bool() != is_signed)
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reject;
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if (inner_add_B->getParam(ID::A_SIGNED).as_bool() != is_signed)
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reject;
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if (inner_add_B->getParam(ID::B_SIGNED).as_bool() != is_signed)
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reject;
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SigSpec pa = inner_add_B->getPort(ID::A);
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SigSpec pb = inner_add_B->getPort(ID::B);
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SigSpec not_y = not_gate_B->getPort(ID::Y);
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auto is_one = [](SigSpec s) {
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if (!s.is_fully_const()) return false;
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Const c = s.as_const();
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for (int i = 0; i < c.size(); i++) {
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if (i == 0 && c[i] != State::S1) return false;
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if (i > 0 && c[i] != State::S0) return false;
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}
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return true;
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};
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bool valid = false;
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if (is_one(pa) && pb == not_y) valid = true;
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if (is_one(pb) && pa == not_y) valid = true;
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if (!valid) reject;
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subtrahend = not_gate_B->getPort(ID::A);
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if (inner_add_B->getPort(ID::Y) == root_add->getPort(ID::A))
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minuend = root_add->getPort(ID::B);
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else
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minuend = root_add->getPort(ID::A);
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// Create the subtraction cell
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log("manual2sub in %s: Found a + (~b + 1) pattern, creating $sub for %s\n", log_id(module), log_signal(result_sig));
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Cell *sub = module->addSub(NEW_ID, minuend, subtrahend, result_sig, is_signed);
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// Let fixup_parameters handle width adjustments
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sub->fixup_parameters();
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// Remove old cells
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autoremove(root_add);
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autoremove(inner_add_B);
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autoremove(not_gate_B);
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did_something = true;
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accept;
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}
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endcode
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@ -0,0 +1,59 @@
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pattern muxneg
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//
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// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
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//
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// Factor negation out of mux
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//
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// s ? (-a) : (-b) ===> -(s ? a : b)
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//
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state <SigSpec> mux_a mux_b mux_s mux_y neg_a_in neg_b_in
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state <bool> neg_a_signed neg_b_signed
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match mux
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select mux->type == $mux
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set mux_a port(mux, \A)
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set mux_b port(mux, \B)
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set mux_s port(mux, \S)
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set mux_y port(mux, \Y)
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endmatch
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match neg_a
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select neg_a->type == $neg
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select nusers(port(neg_a, \Y)) == 2
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index <SigSpec> port(neg_a, \Y) === mux_a
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set neg_a_in port(neg_a, \A)
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set neg_a_signed neg_a->getParam(\A_SIGNED).as_bool()
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endmatch
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match neg_b
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select neg_b->type == $neg
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select nusers(port(neg_b, \Y)) == 2
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index <SigSpec> port(neg_b, \Y) === mux_b
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set neg_b_in port(neg_b, \A)
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set neg_b_signed neg_b->getParam(\A_SIGNED).as_bool()
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endmatch
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code mux_a mux_b mux_s mux_y neg_a_in neg_b_in neg_a_signed neg_b_signed
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if (neg_a_signed != neg_b_signed)
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reject;
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{
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int width = GetSize(mux_y);
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SigSpec mux_out = module->addWire(NEW_ID, width);
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Cell *new_mux = module->addMux(NEW_ID, neg_a_in, neg_b_in, mux_s, mux_out);
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Cell *new_neg = module->addNeg(NEW_ID, mux_out, mux_y, neg_a_signed);
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log("muxneg pattern in %s: mux=%s, neg_a=%s, neg_b=%s\n",
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log_id(module), log_id(mux), log_id(neg_a), log_id(neg_b));
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new_mux->fixup_parameters();
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new_neg->fixup_parameters();
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autoremove(mux);
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autoremove(neg_a);
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autoremove(neg_b);
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did_something = true;
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}
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accept;
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endcode
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@ -0,0 +1,60 @@
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pattern neg2sub
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//
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// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
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//
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// Convert addition with negation back to subtraction
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//
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// a + (-b) ===> a - b
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//
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state <SigSpec> add_a add_b add_y neg_a
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state <bool> add_a_signed add_b_signed neg_signed
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state <bool> neg_on_a
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match add
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select add->type == $add
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set add_a port(add, \A)
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set add_b port(add, \B)
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set add_y port(add, \Y)
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set add_a_signed add->getParam(\A_SIGNED).as_bool()
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set add_b_signed add->getParam(\B_SIGNED).as_bool()
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endmatch
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code neg_on_a
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neg_on_a = true;
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branch;
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neg_on_a = false;
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endcode
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match neg
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select neg->type == $neg
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select nusers(port(neg, \Y)) == 2
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index <SigSpec> port(neg, \Y) === (neg_on_a ? add_a : add_b)
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set neg_a port(neg, \A)
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set neg_signed neg->getParam(\A_SIGNED).as_bool()
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endmatch
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code add_a add_b add_y neg_a neg_on_a add_a_signed add_b_signed neg_signed
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if (add_a_signed != add_b_signed)
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reject;
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if (neg_signed != (neg_on_a ? add_a_signed : add_b_signed))
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reject;
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{
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Cell *new_sub;
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if (neg_on_a)
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new_sub = module->addSub(NEW_ID, add_b, neg_a, add_y, add_b_signed);
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else
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new_sub = module->addSub(NEW_ID, add_a, neg_a, add_y, add_a_signed);
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log("neg2sub pattern in %s: add=%s, neg=%s\n",
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log_id(module), log_id(add), log_id(neg));
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new_sub->fixup_parameters();
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autoremove(add);
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autoremove(neg);
|
||||
did_something = true;
|
||||
}
|
||||
accept;
|
||||
endcode
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
pattern negexpand
|
||||
//
|
||||
// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
|
||||
//
|
||||
// Expand negation over addition
|
||||
//
|
||||
// -(a + b) ===> (-a) + (-b)
|
||||
//
|
||||
|
||||
state <SigSpec> neg_a neg_y add_a add_b
|
||||
state <bool> a_signed
|
||||
|
||||
match neg
|
||||
select neg->type == $neg
|
||||
set neg_a port(neg, \A)
|
||||
set neg_y port(neg, \Y)
|
||||
set a_signed neg->getParam(\A_SIGNED).as_bool()
|
||||
endmatch
|
||||
|
||||
match add
|
||||
select add->type == $add
|
||||
index <SigSpec> port(add, \Y) === neg_a
|
||||
select nusers(port(add, \Y)) == 2
|
||||
set add_a port(add, \A)
|
||||
set add_b port(add, \B)
|
||||
endmatch
|
||||
|
||||
code neg_a neg_y add_a add_b a_signed
|
||||
if (add->getParam(\A_SIGNED).as_bool() != a_signed)
|
||||
reject;
|
||||
if (add->getParam(\B_SIGNED).as_bool() != a_signed)
|
||||
reject;
|
||||
|
||||
{
|
||||
// Use output width for negations to handle overflow correctly
|
||||
int width = GetSize(neg_y);
|
||||
SigSpec neg_add_a = module->addWire(NEW_ID, width);
|
||||
Cell *neg_a_cell = module->addNeg(NEW_ID, add_a, neg_add_a, a_signed);
|
||||
|
||||
SigSpec neg_add_b = module->addWire(NEW_ID, width);
|
||||
Cell *neg_b_cell = module->addNeg(NEW_ID, add_b, neg_add_b, a_signed);
|
||||
|
||||
Cell *new_add = module->addAdd(NEW_ID, neg_add_a, neg_add_b, neg_y, a_signed);
|
||||
|
||||
log("negexpand pattern in %s: neg=%s, add=%s\n",
|
||||
log_id(module), log_id(neg), log_id(add));
|
||||
|
||||
neg_a_cell->fixup_parameters();
|
||||
neg_b_cell->fixup_parameters();
|
||||
new_add->fixup_parameters();
|
||||
autoremove(neg);
|
||||
autoremove(add);
|
||||
did_something = true;
|
||||
}
|
||||
accept;
|
||||
endcode
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
pattern negmux
|
||||
//
|
||||
// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
|
||||
//
|
||||
// Distribute negation over mux
|
||||
//
|
||||
// -(s ? a : b) ===> s ? (-a) : (-b)
|
||||
//
|
||||
|
||||
state <SigSpec> neg_a neg_y mux_a mux_b mux_s
|
||||
state <bool> a_signed
|
||||
|
||||
match neg
|
||||
select neg->type == $neg
|
||||
set neg_a port(neg, \A)
|
||||
set neg_y port(neg, \Y)
|
||||
set a_signed neg->getParam(\A_SIGNED).as_bool()
|
||||
endmatch
|
||||
|
||||
match mux
|
||||
select mux->type == $mux
|
||||
index <SigSpec> port(mux, \Y) === neg_a
|
||||
select nusers(port(mux, \Y)) == 2
|
||||
set mux_a port(mux, \A)
|
||||
set mux_b port(mux, \B)
|
||||
set mux_s port(mux, \S)
|
||||
endmatch
|
||||
|
||||
code neg_a neg_y mux_a mux_b mux_s a_signed
|
||||
{
|
||||
int width = GetSize(neg_y);
|
||||
|
||||
SigSpec neg_mux_a = module->addWire(NEW_ID, width);
|
||||
Cell *neg_a_cell = module->addNeg(NEW_ID, mux_a, neg_mux_a, a_signed);
|
||||
|
||||
SigSpec neg_mux_b = module->addWire(NEW_ID, width);
|
||||
Cell *neg_b_cell = module->addNeg(NEW_ID, mux_b, neg_mux_b, a_signed);
|
||||
|
||||
Cell *new_mux = module->addMux(NEW_ID, neg_mux_a, neg_mux_b, mux_s, neg_y);
|
||||
|
||||
log("negmux pattern in %s: neg=%s, mux=%s\n",
|
||||
log_id(module), log_id(neg), log_id(mux));
|
||||
|
||||
neg_a_cell->fixup_parameters();
|
||||
neg_b_cell->fixup_parameters();
|
||||
new_mux->fixup_parameters();
|
||||
autoremove(neg);
|
||||
autoremove(mux);
|
||||
did_something = true;
|
||||
}
|
||||
accept;
|
||||
endcode
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
pattern negneg
|
||||
//
|
||||
// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
|
||||
//
|
||||
// Simplify double negation
|
||||
//
|
||||
// -(-a) ===> a
|
||||
//
|
||||
|
||||
state <SigSpec> neg1_a neg1_y neg2_a
|
||||
|
||||
match neg1
|
||||
select neg1->type == $neg
|
||||
set neg1_a port(neg1, \A)
|
||||
set neg1_y port(neg1, \Y)
|
||||
endmatch
|
||||
|
||||
match neg2
|
||||
select neg2->type == $neg
|
||||
index <SigSpec> port(neg2, \Y) === neg1_a
|
||||
select nusers(port(neg2, \Y)) == 2
|
||||
set neg2_a port(neg2, \A)
|
||||
endmatch
|
||||
|
||||
code neg1_a neg1_y neg2_a
|
||||
module->connect(neg1_y, neg2_a);
|
||||
|
||||
log("negneg pattern in %s: neg1=%s, neg2=%s\n",
|
||||
log_id(module), log_id(neg1), log_id(neg2));
|
||||
|
||||
autoremove(neg1);
|
||||
autoremove(neg2);
|
||||
did_something = true;
|
||||
accept;
|
||||
endcode
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
pattern negrebuild
|
||||
//
|
||||
// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
|
||||
//
|
||||
// Rebuild addition of negations into negation of addition
|
||||
//
|
||||
// (-a) + (-b) ===> -(a + b)
|
||||
//
|
||||
|
||||
state <SigSpec> add_a add_b add_y neg1_a neg2_a
|
||||
state <bool> add_signed add_b_signed neg1_signed neg2_signed
|
||||
|
||||
match add
|
||||
select add->type == $add
|
||||
set add_a port(add, \A)
|
||||
set add_b port(add, \B)
|
||||
set add_y port(add, \Y)
|
||||
set add_signed add->getParam(\A_SIGNED).as_bool()
|
||||
set add_b_signed add->getParam(\B_SIGNED).as_bool()
|
||||
endmatch
|
||||
|
||||
match neg1
|
||||
select neg1->type == $neg
|
||||
select nusers(port(neg1, \Y)) == 2
|
||||
index <SigSpec> port(neg1, \Y) === add_a
|
||||
set neg1_a port(neg1, \A)
|
||||
set neg1_signed neg1->getParam(\A_SIGNED).as_bool()
|
||||
endmatch
|
||||
|
||||
match neg2
|
||||
select neg2->type == $neg
|
||||
select nusers(port(neg2, \Y)) == 2
|
||||
index <SigSpec> port(neg2, \Y) === add_b
|
||||
set neg2_a port(neg2, \A)
|
||||
set neg2_signed neg2->getParam(\A_SIGNED).as_bool()
|
||||
endmatch
|
||||
|
||||
code add_a add_b add_y neg1_a neg2_a add_signed add_b_signed neg1_signed neg2_signed
|
||||
if (add_signed != add_b_signed)
|
||||
reject;
|
||||
|
||||
if (neg1_signed != add_signed || neg2_signed != add_signed)
|
||||
reject;
|
||||
|
||||
{
|
||||
int width = GetSize(add_y);
|
||||
|
||||
SigSpec sum = module->addWire(NEW_ID, width);
|
||||
Cell *new_add = module->addAdd(NEW_ID, neg1_a, neg2_a, sum, add_signed);
|
||||
Cell *new_neg = module->addNeg(NEW_ID, sum, add_y, add_signed);
|
||||
|
||||
log("negrebuild pattern in %s: add=%s, neg1=%s, neg2=%s\n",
|
||||
log_id(module), log_id(add), log_id(neg1), log_id(neg2));
|
||||
|
||||
new_add->fixup_parameters();
|
||||
new_neg->fixup_parameters();
|
||||
autoremove(add);
|
||||
autoremove(neg1);
|
||||
autoremove(neg2);
|
||||
did_something = true;
|
||||
}
|
||||
accept;
|
||||
endcode
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
pattern sub2neg
|
||||
//
|
||||
// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
|
||||
//
|
||||
// Convert subtraction to addition with negation
|
||||
//
|
||||
// a - b ===> a + (-b)
|
||||
//
|
||||
|
||||
state <SigSpec> sub_a sub_b sub_y
|
||||
state <bool> a_signed b_signed
|
||||
|
||||
match sub
|
||||
select sub->type == $sub
|
||||
filter !sub->getPort(\B).is_fully_const()
|
||||
set sub_a port(sub, \A)
|
||||
set sub_b port(sub, \B)
|
||||
set sub_y port(sub, \Y)
|
||||
set a_signed sub->getParam(\A_SIGNED).as_bool()
|
||||
set b_signed sub->getParam(\B_SIGNED).as_bool()
|
||||
endmatch
|
||||
|
||||
code sub_a sub_b sub_y a_signed b_signed
|
||||
if (a_signed != b_signed)
|
||||
reject;
|
||||
|
||||
{
|
||||
int width = GetSize(sub_y);
|
||||
SigSpec neg_y = module->addWire(NEW_ID, width);
|
||||
Cell *neg = module->addNeg(NEW_ID, sub_b, neg_y, b_signed);
|
||||
Cell *add = module->addAdd(NEW_ID, sub_a, neg_y, sub_y, a_signed);
|
||||
|
||||
log("sub2neg pattern in %s: sub=%s -> neg=%s, add=%s\n",
|
||||
log_id(module), log_id(sub), log_id(neg), log_id(add));
|
||||
|
||||
neg->fixup_parameters();
|
||||
add->fixup_parameters();
|
||||
autoremove(sub);
|
||||
did_something = true;
|
||||
}
|
||||
accept;
|
||||
endcode
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
log -header "Positive case: (a + ~b) + 1 => a - b => a + (-b)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y);
|
||||
input wire [7:0] a;
|
||||
input wire [7:0] b;
|
||||
output wire [7:0] y;
|
||||
|
||||
assign y = (a + ~b) + 1;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$neg
|
||||
select -assert-none t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Positive case B: 1 + (a + ~b) => a - b => a + (-b)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y);
|
||||
input wire [7:0] a;
|
||||
input wire [7:0] b;
|
||||
output wire [7:0] y;
|
||||
|
||||
assign y = 1 + (a + ~b);
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$neg
|
||||
select -assert-none t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative case: fanout on inner add output"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y, z);
|
||||
input wire [7:0] a;
|
||||
input wire [7:0] b;
|
||||
output wire [7:0] y;
|
||||
output wire [7:0] z;
|
||||
(* keep *) wire [7:0] s;
|
||||
assign s = a + ~b;
|
||||
assign y = s + 1;
|
||||
assign z = s + a;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
# Should NOT transform due to fanout on inner add output (marked with keep)
|
||||
select -assert-count 3 t:$add
|
||||
select -assert-count 1 t:$not
|
||||
select -assert-none t:$sub
|
||||
select -assert-none t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
log -header "Simple positive case"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, s, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
input wire s;
|
||||
output wire signed [7:0] y;
|
||||
assign y = s ? (-a) : (-b);
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert negopt -post
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mux
|
||||
select -assert-count 1 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "With intermediate signals"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, s, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
input wire s;
|
||||
output wire signed [7:0] y;
|
||||
wire signed [7:0] neg_a;
|
||||
wire signed [7:0] neg_b;
|
||||
assign neg_a = -a;
|
||||
assign neg_b = -b;
|
||||
assign y = s ? neg_a : neg_b;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -post
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mux
|
||||
select -assert-count 1 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
log -header "Simple positive case (negation on port B)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
output wire signed [8:0] y;
|
||||
assign y = a + (-b);
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -post
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$sub
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Positive case (negation on port A)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
output wire signed [8:0] y;
|
||||
assign y = (-a) + b;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -post
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$sub
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
log -header "Simple positive case (same width)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
output wire signed [7:0] y;
|
||||
assign y = -(a + b);
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 2 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Width extension case (output wider than inputs)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
output wire signed [9:0] y;
|
||||
assign y = -(a + b);
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
# Negations should use output width (9 bits) not input width (8 bits)
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 2 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative case: fanout on add output"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y, z);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
output wire signed [7:0] y;
|
||||
output wire signed [7:0] z;
|
||||
(* keep *) wire signed [7:0] sum;
|
||||
assign sum = a + b;
|
||||
assign y = -sum;
|
||||
assign z = sum;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
# Should NOT transform due to extra fanout on add output
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
log -header "Simple positive case"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, s, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
input wire s;
|
||||
output wire signed [7:0] y;
|
||||
assign y = -(s ? a : b);
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mux
|
||||
select -assert-count 2 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "With intermediate signal"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, s, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
input wire s;
|
||||
output wire signed [7:0] y;
|
||||
wire signed [7:0] m;
|
||||
assign m = s ? a : b;
|
||||
assign y = -m;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mux
|
||||
select -assert-count 2 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative case: mux output has extra fanout"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, s, y, z);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
input wire s;
|
||||
output wire signed [7:0] y;
|
||||
output wire signed [7:0] z;
|
||||
(* keep *) wire signed [7:0] m;
|
||||
assign m = s ? a : b;
|
||||
assign y = -m;
|
||||
assign z = m;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
# Should NOT transform due to extra fanout on mux output
|
||||
select -assert-count 1 t:$mux
|
||||
select -assert-count 1 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
log -header "Simple positive case"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, y);
|
||||
input wire signed [7:0] a;
|
||||
output wire signed [7:0] y;
|
||||
assign y = -(-a);
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
select -assert-none t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "With intermediate signal"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, y);
|
||||
input wire signed [7:0] a;
|
||||
output wire signed [7:0] y;
|
||||
wire signed [7:0] neg_a;
|
||||
assign neg_a = -a;
|
||||
assign y = -neg_a;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
select -assert-none t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative case: extra fanout on inner neg"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, y, z);
|
||||
input wire signed [7:0] a;
|
||||
output wire signed [7:0] y;
|
||||
output wire signed [7:0] z;
|
||||
(* keep *) wire signed [7:0] neg_a;
|
||||
assign neg_a = -a;
|
||||
assign y = -neg_a;
|
||||
assign z = neg_a;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
# Should NOT transform due to extra fanout on inner neg output
|
||||
select -assert-count 2 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
log -header "Simple positive case (same width)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
output wire signed [7:0] y;
|
||||
assign y = (-a) + (-b);
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt
|
||||
check -assert
|
||||
equiv_opt -assert negopt -post
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
log -header "Simple positive case"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, b, y);
|
||||
input wire signed [7:0] a;
|
||||
input wire signed [7:0] b;
|
||||
output wire signed [7:0] y;
|
||||
assign y = a - b;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$neg
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative case: constant subtrahend"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(a, y);
|
||||
input wire signed [7:0] a;
|
||||
output wire signed [7:0] y;
|
||||
assign y = a - 8'd5;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert negopt -pre
|
||||
design -load postopt
|
||||
# Should NOT transform because constant subtraction is kept as $sub
|
||||
select -assert-count 1 t:$sub
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$neg
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Reference in New Issue