mirror of https://github.com/YosysHQ/yosys.git
Added caching of simulation runs for speed
This commit is contained in:
AdvaySingh1
parent
dc4ca2c621
commit
efcabb270f
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@ -98,7 +98,7 @@ void profileFlipFlops(Module *module, const std::string &filename, const std::st
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// Configuration
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static const int DEFAULT_MAX_COVER = 100; // Max candidate signals to consider
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static const int DEFAULT_MIN_REGS = 10; // Min registers per clock gate
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static const int DEFAULT_SIM_ITERATIONS = 10; // Random simulation iterations for pruning
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static const int DEFAULT_SIM_ITERATIONS = 1000; // Random simulation iterations for pruning
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struct SatClockgateWorker
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{
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@ -120,8 +120,8 @@ struct SatClockgateWorker
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ezSatPtr ez;
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SatGen satgen;
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// Random number generator for simulation
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std::mt19937 rng;
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// Cached simulation results: [iteration][SigBit] = evaluated State
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std::vector<dict<SigBit, State>> cached_sim_results;
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// Statistics
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int accepted_count = 0;
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@ -131,7 +131,7 @@ struct SatClockgateWorker
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SatClockgateWorker(Module *module, int max_cover, int min_regs, int sim_iterations)
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: module(module), sigmap(module),
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max_cover(max_cover), min_regs(min_regs), sim_iterations(sim_iterations),
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ez(), satgen(ez.get(), &sigmap), rng(42)
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ez(), satgen(ez.get(), &sigmap)
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{
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// Build driver and sink maps
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for (auto cell : module->cells()) {
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@ -156,16 +156,14 @@ struct SatClockgateWorker
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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satgen.importCell(cell);
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}
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// Run simulation with random inputs using ConstEval
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// Returns false if counterexample found (candidate is definitely invalid)
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bool simulationTest(const std::vector<SigBit> &conds, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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// Pre-run simulations and cache all signal values
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std::mt19937 rng(42);
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cached_sim_results.resize(sim_iterations);
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for (int iter = 0; iter < sim_iterations; iter++) {
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ConstEval ce(module);
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// Generate random values for all input ports
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// Set random values for input ports
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for (auto wire : module->wires()) {
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if (wire->port_input) {
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Const rand_val(State::S0, wire->width);
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@ -174,8 +172,7 @@ struct SatClockgateWorker
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ce.set(SigSpec(wire), rand_val);
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}
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}
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// Randomize FF Q outputs (they're inputs to combinational logic)
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// Set random values for FF Q outputs
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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@ -189,45 +186,55 @@ struct SatClockgateWorker
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}
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}
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// Evaluate gating condition signals
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// Evaluate and cache ALL wire signals
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for (auto wire : module->wires()) {
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for (int i = 0; i < wire->width; i++) {
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SigBit bit(wire, i);
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SigSpec sig(bit);
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if (ce.eval(sig))
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cached_sim_results[iter][sigmap(bit)] = sig[0].data;
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}
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}
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}
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}
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// Check cached simulation results for counterexamples
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// Returns false if counterexample found (candidate is definitely invalid)
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bool simulationTest(const std::vector<SigBit> &conds, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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for (int iter = 0; iter < sim_iterations; iter++) {
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auto &cache = cached_sim_results[iter];
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// Lookup gating condition from cache
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bool combined_cond;
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if (as_enable) {
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combined_cond = false;
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for (auto bit : conds) {
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SigSpec sig(bit);
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if (ce.eval(sig)) {
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if (sig[0] == State::S1)
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combined_cond = true;
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}
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SigBit mapped = sigmap(bit);
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if (cache.count(mapped) && cache[mapped] == State::S1)
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combined_cond = true;
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}
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} else {
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combined_cond = true;
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for (auto bit : conds) {
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SigSpec sig(bit);
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if (ce.eval(sig)) {
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if (sig[0] != State::S1)
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combined_cond = false;
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} else {
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SigBit mapped = sigmap(bit);
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if (!cache.count(mapped) || cache[mapped] != State::S1)
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combined_cond = false;
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}
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}
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}
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bool gating_active = as_enable ? !combined_cond : combined_cond;
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// Evaluate D and Q, check if D != Q
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SigSpec d_eval = sig_d;
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SigSpec q_eval = sig_q;
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bool d_ok = ce.eval(d_eval);
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bool q_ok = ce.eval(q_eval);
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// Lookup D and Q from cache, check if D != Q
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bool d_ne_q = false;
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if (d_ok && q_ok) {
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for (int i = 0; i < sig_d.size(); i++) {
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if (d_eval[i] != q_eval[i]) {
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d_ne_q = true;
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break;
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}
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for (int i = 0; i < sig_d.size(); i++) {
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SigBit d_bit = sigmap(sig_d[i]);
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SigBit q_bit = sigmap(sig_q[i]);
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State d_val = cache.count(d_bit) ? cache[d_bit] : State::S0;
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State q_val = cache.count(q_bit) ? cache[q_bit] : State::S0;
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if (d_val != q_val) {
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d_ne_q = true;
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break;
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}
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}
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