mirror of https://github.com/YosysHQ/yosys.git
Added initial simulation. Incorrect simulation -- changed the number of accedpted results as well as increasing runtime
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AdvaySingh1
parent
2212d85626
commit
e755f6c42e
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@ -23,6 +23,7 @@
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#include <queue>
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#include <algorithm>
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#include <fstream>
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#include <random>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -118,6 +119,10 @@ struct SatClockgateWorker
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ezSatPtr ez;
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SatGen satgen;
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// Simulation infrastructure
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std::vector<Cell*> topo_order; // Cells in topological order for simulation
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std::mt19937 rng; // Random number generator
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// Statistics
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int accepted_count = 0;
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int rejected_sim_count = 0;
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@ -126,7 +131,7 @@ struct SatClockgateWorker
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SatClockgateWorker(Module *module, int max_cover, int min_regs, int sim_iterations)
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: module(module), sigmap(module),
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max_cover(max_cover), min_regs(min_regs), sim_iterations(sim_iterations),
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ez(), satgen(ez.get(), &sigmap)
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ez(), satgen(ez.get(), &sigmap), rng(42)
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{
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// Build driver and sink maps
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for (auto cell : module->cells()) {
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@ -151,6 +156,233 @@ struct SatClockgateWorker
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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satgen.importCell(cell);
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// Build topological order for simulation
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buildTopoOrder();
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}
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// Build topological order of combinational cells for simulation
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void buildTopoOrder()
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{
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dict<Cell*, int> cell_deps; // Number of unresolved input dependencies
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dict<SigBit, pool<Cell*>> bit_to_cells; // Which cells need this bit
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for (auto cell : module->cells()) {
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// Skip FFs
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if (cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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continue;
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int deps = 0;
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for (auto &conn : cell->connections()) {
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if (cell->input(conn.first)) {
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for (auto bit : sigmap(conn.second)) {
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if (bit.wire && sig_to_driver.count(bit)) {
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Cell *driver = sig_to_driver[bit];
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if (!driver->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_))) {
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deps++;
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bit_to_cells[bit].insert(cell);
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}
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}
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}
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}
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}
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cell_deps[cell] = deps;
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}
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// Kahn's algorithm
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std::queue<Cell*> ready;
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for (auto &[cell, deps] : cell_deps) {
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if (deps == 0)
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ready.push(cell);
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}
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while (!ready.empty()) {
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Cell *cell = ready.front();
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ready.pop();
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topo_order.push_back(cell);
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// Decrement deps for cells that depend on this cell's outputs
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for (auto &conn : cell->connections()) {
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if (cell->output(conn.first)) {
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for (auto bit : sigmap(conn.second)) {
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for (auto sink : bit_to_cells[bit]) {
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if (--cell_deps[sink] == 0)
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ready.push(sink);
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}
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}
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}
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}
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}
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}
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// Evaluate a single cell given current simulation values
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void evaluateCell(Cell *cell, dict<SigBit, bool> &sim_values)
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{
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auto getSigVal = [&](SigSpec sig) -> std::vector<bool> {
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std::vector<bool> vals;
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for (auto bit : sigmap(sig)) {
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if (bit.wire) {
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vals.push_back(sim_values.count(bit) ? sim_values[bit] : false);
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} else {
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vals.push_back(bit.data == State::S1);
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}
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}
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return vals;
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};
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auto setSigVal = [&](SigSpec sig, const std::vector<bool> &vals) {
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int i = 0;
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for (auto bit : sigmap(sig)) {
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if (bit.wire && i < (int)vals.size())
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sim_values[bit] = vals[i];
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i++;
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}
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};
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if (cell->type == ID($not) || cell->type == ID($_NOT_)) {
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auto a = getSigVal(cell->getPort(ID::A));
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std::vector<bool> y(a.size());
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for (size_t i = 0; i < a.size(); i++)
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y[i] = !a[i];
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setSigVal(cell->getPort(ID::Y), y);
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}
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else if (cell->type == ID($and) || cell->type == ID($_AND_)) {
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auto a = getSigVal(cell->getPort(ID::A));
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auto b = getSigVal(cell->getPort(ID::B));
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std::vector<bool> y(std::max(a.size(), b.size()));
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for (size_t i = 0; i < y.size(); i++)
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y[i] = (i < a.size() ? a[i] : false) && (i < b.size() ? b[i] : false);
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setSigVal(cell->getPort(ID::Y), y);
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}
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else if (cell->type == ID($or) || cell->type == ID($_OR_)) {
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auto a = getSigVal(cell->getPort(ID::A));
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auto b = getSigVal(cell->getPort(ID::B));
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std::vector<bool> y(std::max(a.size(), b.size()));
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for (size_t i = 0; i < y.size(); i++)
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y[i] = (i < a.size() ? a[i] : false) || (i < b.size() ? b[i] : false);
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setSigVal(cell->getPort(ID::Y), y);
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}
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else if (cell->type == ID($xor) || cell->type == ID($_XOR_)) {
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auto a = getSigVal(cell->getPort(ID::A));
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auto b = getSigVal(cell->getPort(ID::B));
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std::vector<bool> y(std::max(a.size(), b.size()));
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for (size_t i = 0; i < y.size(); i++)
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y[i] = (i < a.size() ? a[i] : false) != (i < b.size() ? b[i] : false);
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setSigVal(cell->getPort(ID::Y), y);
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}
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else if (cell->type == ID($mux) || cell->type == ID($_MUX_)) {
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auto a = getSigVal(cell->getPort(ID::A));
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auto b = getSigVal(cell->getPort(ID::B));
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auto s = getSigVal(cell->getPort(ID::S));
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bool sel = s.empty() ? false : s[0];
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setSigVal(cell->getPort(ID::Y), sel ? b : a);
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}
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else if (cell->type == ID($reduce_and)) {
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auto a = getSigVal(cell->getPort(ID::A));
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bool result = true;
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for (auto v : a) result = result && v;
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setSigVal(cell->getPort(ID::Y), {result});
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}
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else if (cell->type == ID($reduce_or)) {
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auto a = getSigVal(cell->getPort(ID::A));
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bool result = false;
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for (auto v : a) result = result || v;
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setSigVal(cell->getPort(ID::Y), {result});
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}
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else if (cell->type == ID($eq)) {
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auto a = getSigVal(cell->getPort(ID::A));
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auto b = getSigVal(cell->getPort(ID::B));
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bool result = (a == b);
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setSigVal(cell->getPort(ID::Y), {result});
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}
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else if (cell->type == ID($ne)) {
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auto a = getSigVal(cell->getPort(ID::A));
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auto b = getSigVal(cell->getPort(ID::B));
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bool result = (a != b);
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setSigVal(cell->getPort(ID::Y), {result});
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}
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// Add more cell types as needed - for now, unknown cells just pass through
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}
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// Run simulation with random inputs, check if gating_active & (D != Q) is ever true
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// Returns false if counterexample found (candidate is definitely invalid)
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bool simulationTest(const std::vector<SigBit> &conds, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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for (int iter = 0; iter < sim_iterations; iter++) {
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dict<SigBit, bool> sim_values;
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// Initialize all input ports and FF outputs with random values
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for (auto wire : module->wires()) {
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if (wire->port_input) {
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for (int i = 0; i < wire->width; i++)
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sim_values[SigBit(wire, i)] = (rng() & 1);
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}
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}
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// Also randomize FF Q outputs (they're inputs to combinational logic)
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_))) {
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FfData ff(nullptr, cell);
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for (auto bit : sigmap(ff.sig_q))
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if (bit.wire)
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sim_values[bit] = (rng() & 1);
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}
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}
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// Propagate through combinational logic in topological order
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for (auto cell : topo_order)
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evaluateCell(cell, sim_values);
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// Evaluate gating condition
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bool combined_cond;
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if (as_enable) {
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// OR of conditions
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combined_cond = false;
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for (auto bit : conds) {
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SigBit mapped = sigmap(bit);
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if (sim_values.count(mapped) && sim_values[mapped])
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combined_cond = true;
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}
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} else {
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// AND of conditions
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combined_cond = true;
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for (auto bit : conds) {
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SigBit mapped = sigmap(bit);
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if (!sim_values.count(mapped) || !sim_values[mapped])
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combined_cond = false;
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}
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}
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bool gating_active = as_enable ? !combined_cond : combined_cond;
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// Check D != Q
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bool d_ne_q = false;
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for (int i = 0; i < sig_d.size(); i++) {
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SigBit d_bit = sigmap(sig_d[i]);
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SigBit q_bit = sigmap(sig_q[i]);
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bool d_val = sim_values.count(d_bit) ? sim_values[d_bit] : false;
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bool q_val = sim_values.count(q_bit) ? sim_values[q_bit] : false;
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if (d_val != q_val) {
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d_ne_q = true;
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break;
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}
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}
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// If gating is active and D != Q, this is a counterexample
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if (gating_active && d_ne_q) {
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rejected_sim_count++;
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return false;
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}
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}
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return true; // No counterexample found
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}
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// Get downstream signals from a register (BFS forward through combinational logic)
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@ -266,14 +498,6 @@ struct SatClockgateWorker
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return !ez->solve(dummy_exprs, dummy_vals, assumptions);
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}
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// Simple random simulation test to quickly prune candidates
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// bool simulationTest(SigBit candidate, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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// {
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// // For now, skip simulation and go straight to SAT
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// // TODO: Implement random simulation for faster pruning
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// return true;
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// }
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// Binary search to minimize the gating condition set
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// Tries to remove half of the signals at a time
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void minimizeGatingCondition(
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@ -308,11 +532,19 @@ struct SatClockgateWorker
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}
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// Check if OR/AND of signals forms a valid gating condition
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// Uses simulation first to quickly prune invalid candidates, then SAT to prove
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bool isValidGatingSet(const std::vector<SigBit> &conds, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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if (conds.empty())
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return false;
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// Quick simulation filter first - catches most invalid candidates fast
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if (!simulationTest(conds, sig_d, sig_q, as_enable)) {
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log_debug(" Rejected by simulation\n");
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return false;
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}
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// SAT only if simulation passes
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std::vector<int> d_vec = satgen.importSigSpec(sig_d);
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std::vector<int> q_vec = satgen.importSigSpec(sig_q);
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@ -340,7 +572,10 @@ struct SatClockgateWorker
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std::vector<int> dummy_exprs;
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std::vector<bool> dummy_vals;
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return !ez->solve(dummy_exprs, dummy_vals, assumptions);
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bool is_valid = !ez->solve(dummy_exprs, dummy_vals, assumptions);
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if (!is_valid)
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rejected_sat_count++;
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return is_valid;
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}
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// Find gating condition for a register
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@ -395,7 +630,6 @@ struct SatClockgateWorker
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}
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}
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rejected_sat_count++;
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return {{}, false};
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}
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@ -582,8 +816,8 @@ struct SatClockgateWorker
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}
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log(" Inserted %d clock gates\n", gates_inserted);
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log(" Statistics: accepted=%d, rejected_sat=%d\n",
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accepted_count, rejected_sat_count);
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log(" Statistics: accepted=%d, rejected_sim=%d, rejected_sat=%d\n",
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accepted_count, rejected_sim_count, rejected_sat_count);
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log(" SAT stats: literals=%d, expressions=%d\n",
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ez->numLiterals(), ez->numExpressions());
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}
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