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40 Commits

Author SHA1 Message Date
Alessandro Comodi 9be069214f minitest: litepcie: source XRAY_VIVADO_SETTINGS 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-29 20:15:23 +01:00
Alessandro Comodi ab759c7b84 minitest: add/fix gitignore 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-29 19:16:42 +01:00
Alessandro Comodi 924751e0ee minitest: fix litex packages versions 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-29 19:16:42 +01:00
Alessandro Comodi 52d0d87997 minitest: add litepcie minitest 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-29 19:16:42 +01:00
Alessandro Comodi ea5879af18 minitest: litex: litesata: download riscv-gcc as well in Makefile 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-22 16:52:20 +01:00
Alessandro Comodi 730a6518d4 minitest: litex: litesata: add README 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-22 13:42:06 +01:00
Alessandro Comodi f5dfb69d19 minitest: litex: litesata: fix Makefile and build process 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-22 13:42:02 +01:00
Alessandro Comodi 8210db1aa5 minitest: litex: litesata: add make target to get litex 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-22 10:19:29 +01:00
Alessandro Comodi 57a7da706c minitest: add lite-sata minitest to verify GTP status 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-22 10:19:29 +01:00
Tomasz Michalak c66f4f4aa1 Add license headers to tcl files 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak fbf4dd897d Add or fix license header 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 159d6a8e88 Add licensing header to Makefiles 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
litghost f02800daf5
Merge pull request #1218 from antmicro/ddr-uart-bridge 
Added UART DDR minitest
 2020-02-26 17:13:38 -08:00
Tim 'mithro' Ansell 4fbcbb5c87 minitests/litex*: Fix location of clean_json5.py tool. 
Fixes #1255.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-02-24 23:07:48 -08:00
Alessandro Comodi 2f25a2682c ddr-uart: using same design needed in arch-defs for the ddr test 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-12 10:57:34 +01:00
Alessandro Comodi fb5a88a6b8 uart_ddr: improve sdram test script 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-10 15:00:30 +01:00
Alessandro Comodi 51158fd0b8 uart-ddr: addressed review comments and fixed file locations 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-04 11:10:40 +01:00
Alessandro Comodi 8a7e7664f8 uart_ddr: checking out litex at specific commits 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-03 17:17:35 +01:00
Alessandro Comodi 8736d80af3 run make format 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-03 13:08:15 +01:00
Alessandro Comodi f85e244ac6 Added UART DDR minitest 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-03 12:41:40 +01:00
Tomasz Michalak 18acada713 minitests: Add min litex with DDR test 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-12-11 11:49:25 +01:00
Tomasz Michalak fb96f3fe86 minitests: Add minimal Litex configuration for Arty 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-12-10 10:02:36 +01:00
Jake Mercer c05b4b0406 MAKE - Format Trailing Whitespace 
Add `make format-trailing-ws`.  This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-26 10:04:52 +01:00
litghost c94cb0224c
Revert "Whitespace" 2019-10-23 14:22:17 -07:00
Jake Mercer bf11f43390 FORMAT - Run `make format` 
Changes after running `make format`.  Future commits which add
whitespace should be caught by CI at the PR stage.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-22 19:35:24 +01:00
Maciej Kurc 1f31c98265 Updated README.md 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-25 12:13:11 +02:00
Keith Rothman 6c4e6aa718 Update HCLK_IOI offset to match tilegrid 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 17:18:48 -07:00
Keith Rothman 2c7b64ea22 Create script for generating remaining bit report. 
This report is fairly fragile, but works well enough for the remaining
LiteX bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 15:04:29 -07:00
Keith Rothman fa2f61f914 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 17:21:26 -07:00
Keith Rothman a7ba547acb Filter out non-IOB bits. 
Also add output from LiteX to verify IOB FASM features.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 13:38:03 -07:00
Maciej Kurc 68c810ce3b Added source files dependencies to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-25 10:14:20 +02:00
Maciej Kurc 64a05b4fa2 Changed makefiles to use XRAY_DIR 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-19 09:19:28 +02:00
Maciej Kurc bf1c7d3183 Fixed invication of prjxray scripts in Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 13:00:23 +02:00
Maciej Kurc 728a6a76d2 Added bitread and segprint to the Makefile flow 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-17 14:52:06 +02:00
Maciej Kurc 3783e7b2e3 Fixed the LiteX generated SoC to be Linux capable 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-17 13:45:11 +02:00
Maciej Kurc 4798c08ad8 Changed Vivado invocation 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-14 09:40:21 +02:00
Maciej Kurc 4f459cfde3 Ran format-tcl 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:39:49 +02:00
Maciej Kurc 421af109b1 Added bit2fasm targets to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:29:20 +02:00
Maciej Kurc 0c244f242d Added submodule with Yosys and integrated it with the LiteX minitest 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:16:11 +02:00
Maciej Kurc 01f77fd2b2 Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 15:58:06 +02:00