minitest: add lite-sata minitest to verify GTP status

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

minitests/litex/nexys_video_sata/.gitignore

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+# Python data
+src
+
+# Build data
+build*
+sata.*

minitests/litex/nexys_video_sata/Makefile

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+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+SHELL = bash
+
+SYNTH ?= vivado
+YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
+PART = xc7a200tsbg484-1
+PROJECT_NAME = sata
+
+clean:
+	@find . -name "build-par.*" | xargs rm -rf
+	@find . -name "build-syn.*" | xargs rm -rf
+	@rm -f *.edif
+	@rm -f *.bit
+	@rm -f *.bin
+	@rm -f *.log
+	@rm -f *.dcp
+
+help:
+	@echo "Usage: make all [SYNTH=<vivado/yosys>]"
+
+.PHONY: clean help
+
+$(YOSYS):
+	cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc)
+
+build.ok:
+	./src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000
+	touch build/build.ok
+
+VERILOG_FILES = ./build/nexys_video/gateware/nexys_video.v \
+				./src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v
+
+ifeq ($(SYNTH), yosys)
+$(PROJECT_NAME).edif: $(YOSYS) build/build.ok
+	$(YOSYS) -p "read_verilog $(VERILOG_FILES); techmap -map retarget.v; synth_xilinx -flatten -nosrl; write_edif -pvector bra -attrprop $@"  -l $@.log
+
+else ifeq ($(SYNTH), vivado)
+$(PROJECT_NAME).edif: build/build.ok tcl/syn.tcl
+	mkdir -p build-syn.$(basename $@)
+	cd build-syn.$(basename $@) && env PART=$(PART) PROJECT_NAME=$(PROJECT_NAME) $(XRAY_VIVADO) -mode batch -source ../tcl/syn.tcl -nojournal -log ../$@.log
+	rm -rf *.backup.log
+
+endif
+
+$(PROJECT_NAME).bit: $(PROJECT_NAME).edif tcl/par.tcl
+	mkdir -p build-par.$(basename $@)
+	cd build-par.$(basename $@) && env PART=$(PART) PROJECT_NAME=$(PROJECT_NAME) $(XRAY_VIVADO) -mode batch -source ../tcl/par.tcl -nojournal -log ../$@.log
+	rm -rf *.backup.log
+
+$(PROJECT_NAME).fasm: $(PROJECT_NAME).bit
+	source $(XRAY_DIR)/settings/artix7_200t.sh && env XRAY_PART=$(PART) ${XRAY_BIT2FASM} --verbose $(PROJECT_NAME).bit > $(PROJECT_NAME).fasm

minitests/litex/nexys_video_sata/requirements.txt

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+# Litex
+-e git+https://github.com/enjoy-digital/litex#egg=litex
+-e git+https://github.com/enjoy-digital/litedram#egg=litedram
+-e git+https://github.com/enjoy-digital/liteeth#egg=liteeth
+-e git+https://github.com/enjoy-digital/liteiclink#egg=liteiclink
+-e git+https://github.com/enjoy-digital/litejesd204b#egg=litejesd204b
+-e git+https://github.com/enjoy-digital/litepcie#egg=litepcie
+-e git+https://github.com/enjoy-digital/litesata#egg=litesata
+-e git+https://github.com/enjoy-digital/litescope#egg=litescope
+-e git+https://github.com/enjoy-digital/litesdcard#egg=litesdcard
+-e git+https://github.com/enjoy-digital/litevideo#egg=litevideo
+-e git+https://github.com/litex-hub/litehyperbus#egg=litehyperbus
+-e git+https://github.com/litex-hub/litespi#egg=litespi
+-e git+https://github.com/litex-hub/litex-boards#egg=litex_boards
+
+# Migen and nMigen
+-e git+https://github.com/m-labs/migen#egg=migen
+-e git+https://github.com/nmigen/nmigen#egg=nmigen
+
+
+-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv#egg=pythondata_cpu_vexriscv

minitests/litex/nexys_video_sata/retarget.v

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+module FD (output reg Q, input C, D);
+
+parameter [0:0] INIT = 1'b0;
+
+FDRE #(.INIT(INIT)) __TECHMAP_REPLACE__ (.Q(Q), .C(C), .D(D), .CE(1'b1), .R(1'b0));
+
+endmodule
+

minitests/litex/nexys_video_sata/tcl/par.tcl

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+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+create_project -force -name $env(PROJECT_NAME) -part $env(PART)
+
+read_edif ../$env(PROJECT_NAME).edif
+
+link_design -part $env(PART)
+source ../build/nexys_video/gateware/nexys_video.xdc
+
+set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
+set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
+set_property SEVERITY {Warning} [get_drc_checks REQP-1936]
+
+place_design
+route_design
+
+write_checkpoint -force ../$env(PROJECT_NAME).dcp
+
+write_bitstream -force ../$env(PROJECT_NAME).bit

minitests/litex/nexys_video_sata/tcl/syn.tcl

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+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+create_project -force -name $env(PROJECT_NAME) -part $env(XRAY_PART)
+
+read_verilog ../build/nexys_video/gateware/nexys_video.v ../src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v
+
+synth_design -top nexys_video -max_dsp 0
+
+report_timing_summary -file top_timing_synth.rpt
+report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
+report_utilization -file top_utilization_synth.rpt
+
+write_edif -force ../$env(PROJECT_NAME).edif