minitest: add litepcie minitest

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

minitests/litex/litepcie/Makefile

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+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+SHELL = bash
+
+PART = xc7a100tfgg484-2
+PROJECT_NAME = pcie
+RISCV_DIR = riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14
+
+all: $(PROJECT_NAME).fasm
+
+clean:
+	@rm -rf build*
+	@rm -f *.fasm
+
+clean_litex:
+	@rm -rf ${VIRTUAL_ENV}/src
+	@rm -f litex-install.ok
+
+clean_riscv:
+	@rm -rf $(RISCV_DIR)
+	@rm -f riscv-gcc.ok
+
+help:
+	@echo "Usage: make all"
+
+.PHONY: clean help
+
+litex-install.ok:
+	pip install -r requirements.txt
+	touch litex-install.ok
+
+riscv-gcc.ok:
+	wget -qO- https://static.dev.sifive.com/dev-tools/$(RISCV_DIR).tar.gz | tar -xz
+	touch riscv-gcc.ok
+
+build/netv2/gateware/netv2.bit: litex-install.ok riscv-gcc.ok
+	env PATH=${PATH}:${PWD}/${RISCV_DIR}/bin ${VIRTUAL_ENV}/src/litex-boards/litex_boards/targets/netv2.py --with-pcie --variant a7-100 --build
+
+$(PROJECT_NAME).fasm: build/netv2/gateware/netv2.bit
+	source $(XRAY_DIR)/settings/artix7.sh && env XRAY_PART=$(PART) ${XRAY_BIT2FASM} --verbose build/netv2/gateware/netv2.bit > $(PROJECT_NAME).fasm

minitests/litex/litepcie/README.md

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+LitePCIe minitest
+=================
+
+This minitest is intended to provide a counter-prove on the possible remaining features to document for
+the Gigabit Transcievers (GTP tiles) and the PCIE\_2\_1 primitive.
+
+It uses the following litex modules:
+
+| Repo URL                                                  | SHA     |
+| --------------------------------------------------------- | ------- |
+| <https://github.com/enjoy-digital/litex>                  | 7abfbd9 |
+| <https://github.com/enjoy-digital/litedram>               | ab2423e |
+| <https://github.com/enjoy-digital/liteeth>                | 7448170 |
+| <https://github.com/enjoy-digital/liteiclink>             | 0980a7c |
+| <https://github.com/enjoy-digital/litepcie>               | 1d7b584 |
+| <https://github.com/enjoy-digital/litex-boards>           | 1d8f0a9 |
+| <https://github.com/m-labs/migen>                         | 40b1092 |
+| <https://github.com/nmigen/nmigen>                        | 490fca5 |
+| <https://github.com/litex-hub/pythondata-cpu-vexriscv>    | 16c5dde |
+
+The final FASM file with the `unknown bits` can be obtained by running the following:
+
+```bash
+make all
+```
+
+All the pre-requisites (LiteX, RISC-V toolchain, etc.) are automatically installed/built. It is required though to have Vivado installed in the system.

minitests/litex/litepcie/requirements.txt

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+# Litex
+-e git+https://github.com/enjoy-digital/litex@7abfbd9825188d1f6d97453838e18ed7af5526a7#egg=litex
+-e git+https://github.com/enjoy-digital/litedram@ab2423e3dd06783d80fef7aeb43b7c5513c1f2f0#egg=litedram
+-e git+https://github.com/enjoy-digital/liteeth@7448170390ddf4b7c353ae10932377255581c25a#egg=liteeth
+-e git+https://github.com/enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91#egg=liteiclink
+-e git+https://github.com/enjoy-digital/litepcie@01d7b584e8c222ba986b4c8f939d690b9c6f6f7c#egg=litepcie
+-e git+https://github.com/litex-hub/litex-boards@1d8f0a98298e0ed9d5fed08daa7c25aded7ecbb4#egg=litex_boards
+
+# Migen and nMigen
+-e git+https://github.com/m-labs/migen@40b1092a05ec7659c42c8087b0c229dcfb5d9ca1#egg=migen
+-e git+https://github.com/nmigen/nmigen@490fca57457b16421f7b3f2c7812bb229b17744a#egg=nmigen
+
+
+-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv@16c5dded21ca50b73a2bdafab10eeef2ca816818#egg=pythondata_cpu_vexriscv