mirror of https://github.com/openXC7/prjxray.git
Added UART DDR minitest
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
3f0804a417
commit
f85e244ac6
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@ -0,0 +1,90 @@
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# LiteX UART DDR minitest
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This test aims at providing a minimal DDR design.
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The design is tested with a python script that provides memory control signals to the DDR controller
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using an UART bridge.
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The script performs the calbiration process, therfore it looks for the bitslip as well as the delay values.
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### Implementation
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There are two different ways to test this design:
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1. Vivado: the flow is entirely managed by Vivado, including Synthesis. To make use of this flow do the following:
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```
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cd src.vivado
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make
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```
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2. Yosys + Vivado: the flow is divided in two steps. Yosys handles synthesys, while Vivado handles P&R and bitstream generation. To make use of this flow do the following:
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```
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cd src.yosys
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make
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```
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### Testing
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To test the implemented design, load the bitstream produced in the previous step, and do the following:
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1. Open the litex server:
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```
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lxserver --uart --uart-port=/dev/ttyUSBX
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```
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2. On a different terminal, connect to the server through the client script
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```
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cd scripts
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make test_sdram
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```
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#### Output
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Depending on the clock frequency selected during the gateware generation, different outputs are generated:
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- 50 MHz sysytem clock:
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```
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Minimal Arty DDR3 Design for tests with Project X-Ray 2020-02-03 11:30:24
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Release reset
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Bring CKE high
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Load Mode Register 2, CWL=5
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Load Mode Register 3
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Load Mode Register 1
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Load Mode Register 0, CL=6, BL=8
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ZQ Calibration
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bitslip 0: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|31|
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bitslip 1: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 2: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 3: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 4: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 5: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 6: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 7: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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```
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- 100 MHz system clock:
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```
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Minimal Arty DDR3 Design for tests with Project X-Ray 2020-01-31 15:41:14
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Release reset
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Bring CKE high
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Load Mode Register 2, CWL=5
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Load Mode Register 3
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Load Mode Register 1
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Load Mode Register 0, CL=6, BL=8
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ZQ Calibration
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bitslip 0: |00|01|02|03|04|05|06|07|08|09|10|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 1: |..|..|..|..|..|..|..|..|..|..|..|..|..|13|14|15|16|17|18|19|20|21|22|23|24|25|..|..|..|..|..|..|
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bitslip 2: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|29|30|31|
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bitslip 3: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 4: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 5: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 6: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 7: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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```
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@ -0,0 +1 @@
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litex
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litex/litex/tools/litex_client.py:
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git clone https://github.com/enjoy-digital/litex.git
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test_dram: litex/litex/tools/litex_client.py
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./test_sdram.py
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#!/usr/bin/env python3
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.platforms import arty
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from litex.build.xilinx import VivadoProgrammer
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.init import get_sdram_phy_py_header
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self):
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platform = arty.Platform()
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sys_clk_freq = int(50e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "Minimal Arty DDR3 Design for tests with Project X-Ray", ident_version=True,
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cpu_type = None,
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l2_size = 16,
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uart_name = "bridge")
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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sdram_module = MT41K128M16(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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def generate_sdram_phy_py_header(self):
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f = open("sdram_init.py", "w")
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f.write(get_sdram_phy_py_header(
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self.sdram.controller.settings.phy,
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self.sdram.controller.settings.timing))
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f.close()
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# Load ---------------------------------------------------------------------------------------------
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def load():
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prog = VivadoProgrammer()
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prog.load_bitstream("build/gateware/top.bit")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="Minimal Arty DDR3 Design for tests with Project X-Ray")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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args = parser.parse_args()
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if args.load:
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load()
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soc = BaseSoC()
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builder = Builder(soc, output_dir="build", csr_csv="csr.csv")
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builder.build(run=args.build)
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soc.generate_sdram_phy_py_header()
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if __name__ == "__main__":
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main()
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#--------------------------------------------------------------------------------
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# Auto-generated by Migen (--------) & LiteX (3350d33f) on 2020-02-03 11:41:31
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#--------------------------------------------------------------------------------
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csr_base,ctrl,0x82000000,,
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csr_base,identifier_mem,0x82001800,,
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csr_base,timer0,0x82002000,,
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csr_base,ddrphy,0x82002800,,
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csr_base,sdram,0x82004000,,
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csr_register,ctrl_reset,0x82000000,1,rw
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csr_register,ctrl_scratch,0x82000004,4,rw
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csr_register,ctrl_bus_errors,0x82000014,4,ro
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csr_register,timer0_load,0x82002000,4,rw
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csr_register,timer0_reload,0x82002010,4,rw
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csr_register,timer0_en,0x82002020,1,rw
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csr_register,timer0_update_value,0x82002024,1,rw
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csr_register,timer0_value,0x82002028,4,ro
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csr_register,timer0_ev_status,0x82002038,1,rw
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csr_register,timer0_ev_pending,0x8200203c,1,rw
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csr_register,timer0_ev_enable,0x82002040,1,rw
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csr_register,ddrphy_half_sys8x_taps,0x82002800,1,rw
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csr_register,ddrphy_cdly_rst,0x82002804,1,rw
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csr_register,ddrphy_cdly_inc,0x82002808,1,rw
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csr_register,ddrphy_dly_sel,0x8200280c,1,rw
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csr_register,ddrphy_rdly_dq_rst,0x82002810,1,rw
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csr_register,ddrphy_rdly_dq_inc,0x82002814,1,rw
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csr_register,ddrphy_rdly_dq_bitslip_rst,0x82002818,1,rw
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csr_register,ddrphy_rdly_dq_bitslip,0x8200281c,1,rw
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csr_register,sdram_dfii_control,0x82004000,1,rw
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csr_register,sdram_dfii_pi0_command,0x82004004,1,rw
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csr_register,sdram_dfii_pi0_command_issue,0x82004008,1,rw
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csr_register,sdram_dfii_pi0_address,0x8200400c,2,rw
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csr_register,sdram_dfii_pi0_baddress,0x82004014,1,rw
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csr_register,sdram_dfii_pi0_wrdata,0x82004018,4,rw
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csr_register,sdram_dfii_pi0_rddata,0x82004028,4,ro
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csr_register,sdram_dfii_pi1_command,0x82004038,1,rw
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csr_register,sdram_dfii_pi1_command_issue,0x8200403c,1,rw
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csr_register,sdram_dfii_pi1_address,0x82004040,2,rw
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csr_register,sdram_dfii_pi1_baddress,0x82004048,1,rw
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csr_register,sdram_dfii_pi1_wrdata,0x8200404c,4,rw
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csr_register,sdram_dfii_pi1_rddata,0x8200405c,4,ro
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csr_register,sdram_dfii_pi2_command,0x8200406c,1,rw
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csr_register,sdram_dfii_pi2_command_issue,0x82004070,1,rw
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csr_register,sdram_dfii_pi2_address,0x82004074,2,rw
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csr_register,sdram_dfii_pi2_baddress,0x8200407c,1,rw
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csr_register,sdram_dfii_pi2_wrdata,0x82004080,4,rw
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csr_register,sdram_dfii_pi2_rddata,0x82004090,4,ro
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csr_register,sdram_dfii_pi3_command,0x820040a0,1,rw
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csr_register,sdram_dfii_pi3_command_issue,0x820040a4,1,rw
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csr_register,sdram_dfii_pi3_address,0x820040a8,2,rw
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csr_register,sdram_dfii_pi3_baddress,0x820040b0,1,rw
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csr_register,sdram_dfii_pi3_wrdata,0x820040b4,4,rw
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csr_register,sdram_dfii_pi3_rddata,0x820040c4,4,ro
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constant,config_clock_frequency,50000000,,
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constant,config_cpu_type,none,,
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constant,config_cpu_type_none,None,,
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constant,config_csr_alignment,32,,
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constant,config_csr_data_width,8,,
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constant,config_l2_size,32,,
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constant,config_shadow_base,2147483648,,
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memory_region,sram,0x01000000,4096,cached
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memory_region,csr,0x82000000,65536,cached
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memory_region,main_ram,0x40000000,268435456,cached
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dfii_control_sel = 0x01
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dfii_control_cke = 0x02
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dfii_control_odt = 0x04
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dfii_control_reset_n = 0x08
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dfii_command_cs = 0x01
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dfii_command_we = 0x02
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dfii_command_cas = 0x04
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dfii_command_ras = 0x08
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dfii_command_wrdata = 0x10
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dfii_command_rddata = 0x20
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ddrx_mr1 = 0x6
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init_sequence = [
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("Release reset", 0, 0, dfii_control_odt|dfii_control_reset_n, 50000),
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("Bring CKE high", 0, 0, dfii_control_cke|dfii_control_odt|dfii_control_reset_n, 10000),
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("Load Mode Register 2, CWL=5", 512, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 3", 0, 3, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 1", 6, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 0, CL=6, BL=8", 2336, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
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("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200),
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]
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#!/usr/bin/env python3
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import sys
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import time
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from litex import RemoteClient
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from sdram_init import *
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wb = RemoteClient(debug=False)
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wb.open()
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# # #
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# get identifier
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fpga_id = ""
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for i in range(256):
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c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
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fpga_id += c
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if c == "\0":
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break
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print(fpga_id)
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# software control
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wb.regs.sdram_dfii_control.write(0)
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# sdram initialization
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for i, (comment, a, ba, cmd, delay) in enumerate(init_sequence):
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print(comment)
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wb.regs.sdram_dfii_pi0_address.write(a)
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wb.regs.sdram_dfii_pi0_baddress.write(ba)
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if i < 2:
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wb.regs.sdram_dfii_control.write(cmd)
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else:
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wb.regs.sdram_dfii_pi0_command.write(cmd)
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wb.regs.sdram_dfii_pi0_command_issue.write(1)
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# hardware control
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wb.regs.sdram_dfii_control.write(dfii_control_sel)
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def seed_to_data(seed, random=True):
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if random:
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return (1664525*seed + 1013904223) & 0xffffffff
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else:
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return seed
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def write_pattern(length):
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for i in range(length):
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wb.write(wb.mems.main_ram.base + 4*i, seed_to_data(i))
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def check_pattern(length, debug=False):
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errors = 0
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for i in range(length):
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error = 0
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if wb.read(wb.mems.main_ram.base + 4*i) != seed_to_data(i):
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error = 1
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if debug:
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print("{}: 0x{:08x}, 0x{:08x} KO".format(i, wb.read(wb.mems.main_ram.base + 4*i), seed_to_data(i)))
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else:
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if debug:
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print("{}: 0x{:08x}, 0x{:08x} OK".format(i, wb.read(wb.mems.main_ram.base + 4*i), seed_to_data(i)))
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errors += error
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return errors
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# find working bitslips and delays
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nbitslips = 8
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ndelays = 32
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nmodules = 2
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nwords = 16
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for bitslip in range(nbitslips):
|
||||
print("bitslip {:d}: |".format(bitslip), end="")
|
||||
for delay in range(ndelays):
|
||||
for module in range(nmodules):
|
||||
wb.regs.ddrphy_dly_sel.write(1<<module)
|
||||
wb.regs.ddrphy_rdly_dq_rst.write(1)
|
||||
wb.regs.ddrphy_rdly_dq_bitslip_rst.write(1)
|
||||
for i in range(bitslip):
|
||||
wb.regs.ddrphy_rdly_dq_bitslip.write(1)
|
||||
for i in range(delay):
|
||||
wb.regs.ddrphy_rdly_dq_inc.write(1)
|
||||
write_pattern(nwords)
|
||||
errors = check_pattern(nwords)
|
||||
if errors:
|
||||
print("..|", end="")
|
||||
else:
|
||||
print("{:02d}|".format(delay), end="")
|
||||
sys.stdout.flush()
|
||||
print("")
|
||||
|
||||
# # #
|
||||
|
||||
wb.close()
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
PART = xc7a35tcsg324-1
|
||||
BIT2FASM_ARGS = --part "$(XRAY_DIR)/database/artix7/$(PART)" --verbose
|
||||
SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/top.v
|
||||
|
||||
all: top.fasm top.bits segprint.log
|
||||
|
||||
clean:
|
||||
@rm -f *.bit
|
||||
@rm -f *.bin
|
||||
@rm -f *.bits
|
||||
@rm -f *.fasm
|
||||
@rm -f *.log
|
||||
@rm -rf build
|
||||
|
||||
.PHONY: all clean
|
||||
|
||||
top.bit: $(VIVADO) $(SOURCES) top.xdc top.tcl
|
||||
mkdir -p build
|
||||
cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
|
||||
cp build/*.bit ./
|
||||
|
||||
top.fasm: top.bit
|
||||
PYTHONPATH="$(XRAY_DIR):$(XRAY_DIR)/utils:$(XRAY_DIR)/third_party/fasm" \
|
||||
PATH="$(XRAY_DIR)/build/tools:$(PATH)" \
|
||||
$(XRAY_BIT2FASM) $(BIT2FASM_ARGS) \
|
||||
top.bit >top.fasm \
|
||||
|| (rm -f top.fasm && exit 1)
|
||||
|
||||
top.bits: top.bit
|
||||
$(XRAY_BITREAD) -part_file $(XRAY_DIR)/database/artix7/$(PART)/part.yaml -o top.bits -z -y top.bit
|
||||
|
||||
segprint.log: top.bits
|
||||
$(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
create_project -force -name top -part xc7a35ticsg324-1L
|
||||
add_files {../../verilog/top.v}
|
||||
read_xdc ../top.xdc
|
||||
synth_design -top top -part xc7a35ticsg324-1L
|
||||
report_timing_summary -file top_timing_synth.rpt
|
||||
report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
|
||||
report_utilization -file top_utilization_synth.rpt
|
||||
opt_design
|
||||
place_design
|
||||
report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
|
||||
report_utilization -file top_utilization_place.rpt
|
||||
report_io -file top_io.rpt
|
||||
report_control_sets -verbose -file top_control_sets.rpt
|
||||
report_clock_utilization -file top_clock_utilization.rpt
|
||||
route_design
|
||||
phys_opt_design
|
||||
report_timing_summary -no_header -no_detailed_paths
|
||||
write_checkpoint -force top_route.dcp
|
||||
report_route_status -file top_route_status.rpt
|
||||
report_drc -file top_drc.rpt
|
||||
report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
|
||||
report_power -file top_power.rpt
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
write_bitstream -force top.bit
|
||||
write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
|
||||
quit
|
||||
|
|
@ -0,0 +1,298 @@
|
|||
################################################################################
|
||||
# IO constraints
|
||||
################################################################################
|
||||
# serial:0.tx
|
||||
set_property LOC D10 [get_ports serial_tx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
|
||||
|
||||
# serial:0.rx
|
||||
set_property LOC A9 [get_ports serial_rx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
|
||||
|
||||
# cpu_reset:0
|
||||
set_property LOC C2 [get_ports cpu_reset]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
|
||||
|
||||
# clk100:0
|
||||
set_property LOC E3 [get_ports clk100]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk100]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC R2 [get_ports ddram_a[0]]
|
||||
set_property SLEW FAST [get_ports ddram_a[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC M6 [get_ports ddram_a[1]]
|
||||
set_property SLEW FAST [get_ports ddram_a[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC N4 [get_ports ddram_a[2]]
|
||||
set_property SLEW FAST [get_ports ddram_a[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC T1 [get_ports ddram_a[3]]
|
||||
set_property SLEW FAST [get_ports ddram_a[3]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC N6 [get_ports ddram_a[4]]
|
||||
set_property SLEW FAST [get_ports ddram_a[4]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC R7 [get_ports ddram_a[5]]
|
||||
set_property SLEW FAST [get_ports ddram_a[5]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC V6 [get_ports ddram_a[6]]
|
||||
set_property SLEW FAST [get_ports ddram_a[6]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC U7 [get_ports ddram_a[7]]
|
||||
set_property SLEW FAST [get_ports ddram_a[7]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC R8 [get_ports ddram_a[8]]
|
||||
set_property SLEW FAST [get_ports ddram_a[8]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC V7 [get_ports ddram_a[9]]
|
||||
set_property SLEW FAST [get_ports ddram_a[9]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC R6 [get_ports ddram_a[10]]
|
||||
set_property SLEW FAST [get_ports ddram_a[10]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC U6 [get_ports ddram_a[11]]
|
||||
set_property SLEW FAST [get_ports ddram_a[11]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC T6 [get_ports ddram_a[12]]
|
||||
set_property SLEW FAST [get_ports ddram_a[12]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC T8 [get_ports ddram_a[13]]
|
||||
set_property SLEW FAST [get_ports ddram_a[13]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
|
||||
|
||||
# ddram:0.ba
|
||||
set_property LOC R1 [get_ports ddram_ba[0]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
|
||||
|
||||
# ddram:0.ba
|
||||
set_property LOC P4 [get_ports ddram_ba[1]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
|
||||
|
||||
# ddram:0.ba
|
||||
set_property LOC P2 [get_ports ddram_ba[2]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
|
||||
|
||||
# ddram:0.ras_n
|
||||
set_property LOC P3 [get_ports ddram_ras_n]
|
||||
set_property SLEW FAST [get_ports ddram_ras_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
|
||||
|
||||
# ddram:0.cas_n
|
||||
set_property LOC M4 [get_ports ddram_cas_n]
|
||||
set_property SLEW FAST [get_ports ddram_cas_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
|
||||
|
||||
# ddram:0.we_n
|
||||
set_property LOC P5 [get_ports ddram_we_n]
|
||||
set_property SLEW FAST [get_ports ddram_we_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
|
||||
|
||||
# ddram:0.cs_n
|
||||
set_property LOC U8 [get_ports ddram_cs_n]
|
||||
set_property SLEW FAST [get_ports ddram_cs_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
|
||||
|
||||
# ddram:0.dm
|
||||
set_property LOC L1 [get_ports ddram_dm[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dm[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
|
||||
|
||||
# ddram:0.dm
|
||||
set_property LOC U1 [get_ports ddram_dm[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dm[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC K5 [get_ports ddram_dq[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC L3 [get_ports ddram_dq[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC K3 [get_ports ddram_dq[2]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC L6 [get_ports ddram_dq[3]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[3]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC M3 [get_ports ddram_dq[4]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[4]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC M1 [get_ports ddram_dq[5]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[5]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC L4 [get_ports ddram_dq[6]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[6]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC M2 [get_ports ddram_dq[7]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[7]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC V4 [get_ports ddram_dq[8]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[8]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC T5 [get_ports ddram_dq[9]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[9]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC U4 [get_ports ddram_dq[10]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[10]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC V5 [get_ports ddram_dq[11]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[11]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC V1 [get_ports ddram_dq[12]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[12]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC T3 [get_ports ddram_dq[13]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[13]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC U3 [get_ports ddram_dq[14]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[14]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC R3 [get_ports ddram_dq[15]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[15]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
|
||||
|
||||
# ddram:0.dqs_p
|
||||
set_property LOC N2 [get_ports ddram_dqs_p[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_p[0]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
|
||||
|
||||
# ddram:0.dqs_p
|
||||
set_property LOC U2 [get_ports ddram_dqs_p[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_p[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
|
||||
|
||||
# ddram:0.dqs_n
|
||||
set_property LOC N1 [get_ports ddram_dqs_n[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[0]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
|
||||
|
||||
# ddram:0.dqs_n
|
||||
set_property LOC V2 [get_ports ddram_dqs_n[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
|
||||
|
||||
# ddram:0.clk_p
|
||||
set_property LOC U9 [get_ports ddram_clk_p]
|
||||
set_property SLEW FAST [get_ports ddram_clk_p]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
|
||||
|
||||
# ddram:0.clk_n
|
||||
set_property LOC V9 [get_ports ddram_clk_n]
|
||||
set_property SLEW FAST [get_ports ddram_clk_n]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
|
||||
|
||||
# ddram:0.cke
|
||||
set_property LOC N5 [get_ports ddram_cke]
|
||||
set_property SLEW FAST [get_ports ddram_cke]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
|
||||
|
||||
# ddram:0.odt
|
||||
set_property LOC R5 [get_ports ddram_odt]
|
||||
set_property SLEW FAST [get_ports ddram_odt]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
|
||||
|
||||
# ddram:0.reset_n
|
||||
set_property LOC K6 [get_ports ddram_reset_n]
|
||||
set_property SLEW FAST [get_ports ddram_reset_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
|
||||
|
||||
################################################################################
|
||||
# Design constraints
|
||||
################################################################################
|
||||
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
|
||||
################################################################################
|
||||
# Clock constraints
|
||||
################################################################################
|
||||
|
||||
|
||||
create_clock -name clk100 -period 10.0 [get_nets clk100]
|
||||
|
||||
################################################################################
|
||||
# False path constraints
|
||||
################################################################################
|
||||
|
||||
|
||||
set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
export XRAY_PART = xc7a35tcsg324-1
|
||||
export XRAY_PART_YAML = $(XRAY_DATABASE_DIR)/$(XRAY_DATABASE)/$(XRAY_PART)/part.yaml
|
||||
YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
|
||||
SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/top.v
|
||||
PORT ?= /dev/ttyUSB1
|
||||
|
||||
all: top.f2b.bit
|
||||
|
||||
clean:
|
||||
@rm -f *.edif
|
||||
@rm -f *.bit
|
||||
@rm -f *.bin
|
||||
@rm -f *.bits
|
||||
@rm -f *.fasm
|
||||
@rm -f *.frames
|
||||
@rm -f *.log
|
||||
@rm -rf build
|
||||
|
||||
.PHONY: all clean
|
||||
|
||||
$(YOSYS):
|
||||
cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc)
|
||||
|
||||
top.edif: $(YOSYS) synth.ys $(SOURCES)
|
||||
$(YOSYS) -s synth.ys -l yosys.log
|
||||
|
||||
top.bit: $(VIVADO) top.edif top.xdc top.tcl
|
||||
mkdir -p build
|
||||
cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
|
||||
python3 $(XRAY_DIR)/minitests/timing/clean_json5.py < build/iobuf_report.json5 > build/iobuf_report.json
|
||||
cp build/*.bit ./
|
||||
|
||||
top.fasm: top.bit
|
||||
$(XRAY_BIT2FASM) --verbose $< > $@ \
|
||||
|| (rm -f top.fasm && exit 1)
|
||||
|
||||
top.bits: top.bit
|
||||
$(XRAY_BITREAD) -part_file $(XRAY_PART_YAML) -o top.bits -z -y top.bit
|
||||
|
||||
segprint.log: top.bits
|
||||
$(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log
|
||||
|
||||
top.frames: top.fasm
|
||||
$(XRAY_FASM2FRAMES) $< $@
|
||||
|
||||
top.f2b.bit: top.frames
|
||||
$(XRAY_DIR)/build/tools/xc7frames2bit --output_file $@ --part_name $(XRAY_PART) --part_file $(XRAY_PART_YAML) --frm_file $<
|
||||
|
||||
program: top.f2b.bit
|
||||
xc3sprog -c nexys4 top.f2b.bit
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
../verilog/mem.init
|
||||
|
|
@ -0,0 +1 @@
|
|||
../verilog/mem_1.init
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
""" Generates a missing feature/bit report for LiteX design.
|
||||
|
||||
This script is fairly fragile, because it depends on the specific observation
|
||||
that all of the remaining bits appear to either belong to HCLK_IOI or IOI3
|
||||
tiles. A more general version of this script could be created, but that was
|
||||
not the point of this script.
|
||||
|
||||
"""
|
||||
from fasm import parse_fasm_filename
|
||||
|
||||
|
||||
def main():
|
||||
fasm_file = 'top.fasm'
|
||||
fasm_model = list(parse_fasm_filename(fasm_file))
|
||||
|
||||
unknown_bits = {
|
||||
'HCLK_IOI': {},
|
||||
'IOI3': {},
|
||||
}
|
||||
|
||||
total_unknown = 0
|
||||
for l in fasm_model:
|
||||
if l.annotations is None:
|
||||
continue
|
||||
|
||||
annotations = {}
|
||||
for annotation in l.annotations:
|
||||
annotations[annotation.name] = annotation.value
|
||||
|
||||
if 'unknown_bit' not in annotations:
|
||||
continue
|
||||
|
||||
total_unknown += 1
|
||||
|
||||
frame, word, bit = annotations['unknown_bit'].split('_')
|
||||
|
||||
frame = int(frame, 16)
|
||||
word = int(word)
|
||||
bit = int(bit)
|
||||
|
||||
frame_offset = frame % 0x80
|
||||
base_frame = frame - frame_offset
|
||||
|
||||
# All remaining LiteX bits appear to be in this one IO bank, so limit
|
||||
# the tool this this one IO bank.
|
||||
assert base_frame == 0x00401580, hex(frame)
|
||||
|
||||
SIZE = 4
|
||||
INITIAL_OFFSET = -2
|
||||
|
||||
if word == 50:
|
||||
group = 'HCLK_IOI'
|
||||
offset = 45
|
||||
elif word < 50:
|
||||
group = 'IOI3'
|
||||
offset = ((word - INITIAL_OFFSET) // SIZE) * SIZE + INITIAL_OFFSET
|
||||
else:
|
||||
group = 'IOI3'
|
||||
word -= 1
|
||||
offset = ((word - INITIAL_OFFSET) // SIZE) * SIZE + INITIAL_OFFSET
|
||||
offset += 1
|
||||
word += 1
|
||||
|
||||
bit = '{}_{:02d}'.format(
|
||||
frame_offset,
|
||||
(word - offset) * 32 + bit,
|
||||
)
|
||||
|
||||
if bit not in unknown_bits[group]:
|
||||
unknown_bits[group][bit] = 0
|
||||
unknown_bits[group][bit] += 1
|
||||
|
||||
print('Total unknown bits: {}'.format(total_unknown))
|
||||
for group in unknown_bits:
|
||||
print('Group {} (count = {}):'.format(group, len(unknown_bits[group])))
|
||||
for bit in sorted(unknown_bits[group]):
|
||||
print(' {} (count = {})'.format(bit, unknown_bits[group][bit]))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
read_verilog ../verilog/top.v
|
||||
synth_xilinx -edif top.edif
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
proc write_iobuf_report {filename} {
|
||||
set fp [open $filename w]
|
||||
puts $fp "{ \"tiles\": \["
|
||||
foreach port [get_ports] {
|
||||
set net [get_nets -of $port]
|
||||
if { $net == "" } {
|
||||
continue
|
||||
}
|
||||
|
||||
set cell [get_cells -of $net]
|
||||
set site [get_sites -of $cell]
|
||||
set tile [get_tiles -of $site]
|
||||
|
||||
puts $fp "{"
|
||||
puts $fp "\"port\": \"$port\","
|
||||
puts $fp "\"pad_wire\": \"$net\","
|
||||
puts $fp "\"cell\": \"$cell\","
|
||||
puts $fp "\"site\": \"$site\","
|
||||
puts $fp "\"tile\": \"$tile\","
|
||||
puts $fp "\"type\": \"[get_property REF_NAME $cell]\","
|
||||
puts $fp "\"IOSTANDARD\": \"\\\"[get_property IOSTANDARD $cell]\\\"\","
|
||||
puts $fp "\"PULLTYPE\": \"\\\"[get_property PULLTYPE $cell]\\\"\","
|
||||
puts $fp "\"DRIVE\": \"[get_property DRIVE $cell]\","
|
||||
puts $fp "\"SLEW\": \"\\\"[get_property SLEW $cell]\\\"\","
|
||||
puts $fp "},"
|
||||
}
|
||||
puts $fp "\]}"
|
||||
close $fp
|
||||
}
|
||||
|
||||
create_project -force -name top -part xc7a35ticsg324-1L
|
||||
read_xdc ../top.xdc
|
||||
read_edif ../top.edif
|
||||
link_design -top top -part xc7a35ticsg324-1L
|
||||
report_timing_summary -file top_timing_synth.rpt
|
||||
report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
|
||||
report_utilization -file top_utilization_synth.rpt
|
||||
opt_design
|
||||
place_design
|
||||
report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
|
||||
report_utilization -file top_utilization_place.rpt
|
||||
report_io -file top_io.rpt
|
||||
report_control_sets -verbose -file top_control_sets.rpt
|
||||
report_clock_utilization -file top_clock_utilization.rpt
|
||||
route_design
|
||||
phys_opt_design
|
||||
report_timing_summary -no_header -no_detailed_paths
|
||||
write_checkpoint -force top_route.dcp
|
||||
report_route_status -file top_route_status.rpt
|
||||
report_drc -file top_drc.rpt
|
||||
report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
|
||||
report_power -file top_power.rpt
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
write_bitstream -force top.bit
|
||||
write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
|
||||
|
||||
write_iobuf_report iobuf_report.json5
|
||||
|
||||
|
||||
quit
|
||||
|
|
@ -0,0 +1,298 @@
|
|||
################################################################################
|
||||
# IO constraints
|
||||
################################################################################
|
||||
# serial:0.tx
|
||||
set_property LOC D10 [get_ports serial_tx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
|
||||
|
||||
# serial:0.rx
|
||||
set_property LOC A9 [get_ports serial_rx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
|
||||
|
||||
# cpu_reset:0
|
||||
set_property LOC C2 [get_ports cpu_reset]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
|
||||
|
||||
# clk100:0
|
||||
set_property LOC E3 [get_ports clk100]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk100]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC R2 [get_ports ddram_a[0]]
|
||||
set_property SLEW FAST [get_ports ddram_a[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC M6 [get_ports ddram_a[1]]
|
||||
set_property SLEW FAST [get_ports ddram_a[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC N4 [get_ports ddram_a[2]]
|
||||
set_property SLEW FAST [get_ports ddram_a[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC T1 [get_ports ddram_a[3]]
|
||||
set_property SLEW FAST [get_ports ddram_a[3]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC N6 [get_ports ddram_a[4]]
|
||||
set_property SLEW FAST [get_ports ddram_a[4]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC R7 [get_ports ddram_a[5]]
|
||||
set_property SLEW FAST [get_ports ddram_a[5]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC V6 [get_ports ddram_a[6]]
|
||||
set_property SLEW FAST [get_ports ddram_a[6]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC U7 [get_ports ddram_a[7]]
|
||||
set_property SLEW FAST [get_ports ddram_a[7]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC R8 [get_ports ddram_a[8]]
|
||||
set_property SLEW FAST [get_ports ddram_a[8]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC V7 [get_ports ddram_a[9]]
|
||||
set_property SLEW FAST [get_ports ddram_a[9]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC R6 [get_ports ddram_a[10]]
|
||||
set_property SLEW FAST [get_ports ddram_a[10]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC U6 [get_ports ddram_a[11]]
|
||||
set_property SLEW FAST [get_ports ddram_a[11]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC T6 [get_ports ddram_a[12]]
|
||||
set_property SLEW FAST [get_ports ddram_a[12]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC T8 [get_ports ddram_a[13]]
|
||||
set_property SLEW FAST [get_ports ddram_a[13]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
|
||||
|
||||
# ddram:0.ba
|
||||
set_property LOC R1 [get_ports ddram_ba[0]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
|
||||
|
||||
# ddram:0.ba
|
||||
set_property LOC P4 [get_ports ddram_ba[1]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
|
||||
|
||||
# ddram:0.ba
|
||||
set_property LOC P2 [get_ports ddram_ba[2]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
|
||||
|
||||
# ddram:0.ras_n
|
||||
set_property LOC P3 [get_ports ddram_ras_n]
|
||||
set_property SLEW FAST [get_ports ddram_ras_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
|
||||
|
||||
# ddram:0.cas_n
|
||||
set_property LOC M4 [get_ports ddram_cas_n]
|
||||
set_property SLEW FAST [get_ports ddram_cas_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
|
||||
|
||||
# ddram:0.we_n
|
||||
set_property LOC P5 [get_ports ddram_we_n]
|
||||
set_property SLEW FAST [get_ports ddram_we_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
|
||||
|
||||
# ddram:0.cs_n
|
||||
set_property LOC U8 [get_ports ddram_cs_n]
|
||||
set_property SLEW FAST [get_ports ddram_cs_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
|
||||
|
||||
# ddram:0.dm
|
||||
set_property LOC L1 [get_ports ddram_dm[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dm[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
|
||||
|
||||
# ddram:0.dm
|
||||
set_property LOC U1 [get_ports ddram_dm[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dm[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC K5 [get_ports ddram_dq[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC L3 [get_ports ddram_dq[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC K3 [get_ports ddram_dq[2]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC L6 [get_ports ddram_dq[3]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[3]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC M3 [get_ports ddram_dq[4]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[4]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC M1 [get_ports ddram_dq[5]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[5]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC L4 [get_ports ddram_dq[6]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[6]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC M2 [get_ports ddram_dq[7]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[7]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC V4 [get_ports ddram_dq[8]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[8]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC T5 [get_ports ddram_dq[9]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[9]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC U4 [get_ports ddram_dq[10]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[10]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC V5 [get_ports ddram_dq[11]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[11]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC V1 [get_ports ddram_dq[12]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[12]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC T3 [get_ports ddram_dq[13]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[13]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC U3 [get_ports ddram_dq[14]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[14]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC R3 [get_ports ddram_dq[15]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[15]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
|
||||
|
||||
# ddram:0.dqs_p
|
||||
set_property LOC N2 [get_ports ddram_dqs_p[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_p[0]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
|
||||
|
||||
# ddram:0.dqs_p
|
||||
set_property LOC U2 [get_ports ddram_dqs_p[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_p[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
|
||||
|
||||
# ddram:0.dqs_n
|
||||
set_property LOC N1 [get_ports ddram_dqs_n[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[0]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
|
||||
|
||||
# ddram:0.dqs_n
|
||||
set_property LOC V2 [get_ports ddram_dqs_n[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
|
||||
|
||||
# ddram:0.clk_p
|
||||
set_property LOC U9 [get_ports ddram_clk_p]
|
||||
set_property SLEW FAST [get_ports ddram_clk_p]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
|
||||
|
||||
# ddram:0.clk_n
|
||||
set_property LOC V9 [get_ports ddram_clk_n]
|
||||
set_property SLEW FAST [get_ports ddram_clk_n]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
|
||||
|
||||
# ddram:0.cke
|
||||
set_property LOC N5 [get_ports ddram_cke]
|
||||
set_property SLEW FAST [get_ports ddram_cke]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
|
||||
|
||||
# ddram:0.odt
|
||||
set_property LOC R5 [get_ports ddram_odt]
|
||||
set_property SLEW FAST [get_ports ddram_odt]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
|
||||
|
||||
# ddram:0.reset_n
|
||||
set_property LOC K6 [get_ports ddram_reset_n]
|
||||
set_property SLEW FAST [get_ports ddram_reset_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
|
||||
|
||||
################################################################################
|
||||
# Design constraints
|
||||
################################################################################
|
||||
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
|
||||
################################################################################
|
||||
# Clock constraints
|
||||
################################################################################
|
||||
|
||||
|
||||
create_clock -name clk100 -period 10.0 [get_nets clk100]
|
||||
|
||||
################################################################################
|
||||
# False path constraints
|
||||
################################################################################
|
||||
|
||||
|
||||
set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
4d
|
||||
69
|
||||
6e
|
||||
69
|
||||
6d
|
||||
61
|
||||
6c
|
||||
20
|
||||
41
|
||||
72
|
||||
74
|
||||
79
|
||||
20
|
||||
44
|
||||
44
|
||||
52
|
||||
33
|
||||
20
|
||||
44
|
||||
65
|
||||
73
|
||||
69
|
||||
67
|
||||
6e
|
||||
20
|
||||
66
|
||||
6f
|
||||
72
|
||||
20
|
||||
74
|
||||
65
|
||||
73
|
||||
74
|
||||
73
|
||||
20
|
||||
77
|
||||
69
|
||||
74
|
||||
68
|
||||
20
|
||||
50
|
||||
72
|
||||
6f
|
||||
6a
|
||||
65
|
||||
63
|
||||
74
|
||||
20
|
||||
58
|
||||
2d
|
||||
52
|
||||
61
|
||||
79
|
||||
20
|
||||
32
|
||||
30
|
||||
32
|
||||
30
|
||||
2d
|
||||
30
|
||||
32
|
||||
2d
|
||||
30
|
||||
33
|
||||
20
|
||||
31
|
||||
31
|
||||
3a
|
||||
33
|
||||
30
|
||||
3a
|
||||
32
|
||||
34
|
||||
0
|
||||
File diff suppressed because one or more lines are too long
Loading…
Reference in New Issue