minitests: Add minimal Litex configuration for Arty

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>

minitests/litex/README.md

@@ -1,10 +1,16 @@
 # LiteX minitest
 
-This folder contains a minitest for a Linux capable LiteX SoC for Arty board.
+This folder contains minitest for various Litex configurations and target platforms.
+It is divided into two directories that differ in the CPU configuration.
+
+* min - Minimal configuration - just a CPU + uart targeting Arty and Basys3 boards. The firmware is compiled into the bitstream i.e. the ROM and SRAM memories are instantiated and initialized on the FPGA (no DDR RAM controller).
+* base - Linux capable SoC configuration with DDR and Ethernet targeting the Arty.
 
 ## Synthesis+implementation
 
-There are two variants: for Vivado only flow and for Yosys+Vivado flow. In order to run one of them enter the specific directory and run `make`.
+For each variant and platform there are two variants: for Vivado only flow and for Yosys+Vivado flow.
+In order to run one of them enter the specific directory and run `make`.
+Once the bitstream is generated and loaded to the board, we should see the test result on the terminal connected to one of the serial ports.
 
 ## HDL code generation
 
@@ -104,4 +110,4 @@ cd litex/litex/boards/targets
 
 You can choose which synthesis tool generate the design for. This can be done via the additional `--synth-mode` option of the `arty.py` script. The default is `vivado` but you can change it and specify `yosys`.
 
-Generated code will be placed in the `litex/litex/boards/targets/soc_ethernetsoc_arty` folder.
+Generated code will be placed in the `litex/litex/boards/targets/soc_ethernetsoc_arty` folder.

minitests/litex/min/arty/scripts/minilitex_arty.py

@@ -0,0 +1,74 @@
+#!/usr/bin/env python3
+
+# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+import argparse
+
+from migen import *
+
+from litex.boards.platforms import arty
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+from litex.soc.cores.clock import *
+
+# CRG ----------------------------------------------------------------------------------------------
+
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.clock_domains.cd_sys = ClockDomain()
+
+        # # #
+
+        self.cd_sys.clk.attr.add("keep")
+
+        self.submodules.pll = pll = S7PLL(speedgrade=-1)
+        self.comb += pll.reset.eq(~platform.request("cpu_reset"))
+        pll_clkin = Signal()
+        pll.register_clkin(pll_clkin, 100e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq)
+
+        self.specials += Instance(
+            "BUFG", i_I=platform.request("clk100"), o_O=pll_clkin)
+
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+
+class BaseSoC(SoCCore):
+    def __init__(
+            self, sys_clk_freq=int(50e6), integrated_rom_size=0x8000,
+            **kwargs):
+        platform = arty.Platform()
+        SoCCore.__init__(
+            self,
+            platform,
+            clk_freq=sys_clk_freq,
+            integrated_rom_size=integrated_rom_size,
+            integrated_sram_size=0x8000,
+            ident="MiniLitex",
+            cpu_variant="lite",
+            **kwargs)
+
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+
+# Build --------------------------------------------------------------------------------------------
+
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
+    builder_args(parser)
+    soc_core_args(parser)
+    args = parser.parse_args()
+
+    cls = BaseSoC
+    soc = cls(**soc_core_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build()
+
+
+if __name__ == "__main__":
+    main()

minitests/litex/min/arty/src.vivado/Makefile

@@ -0,0 +1,40 @@
+export XRAY_PART=xc7a35tcsg324-1
+export XRAY_PART_YAML=$(XRAY_DATABASE_DIR)/$(XRAY_DATABASE)/$(XRAY_PART).yaml
+SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/mem_2.init ../verilog/top.v ../verilog/VexRiscv_Lite.v
+
+all: top.f2b.bit
+
+clean:
+	@rm -f *.bit
+	@rm -f *.bin
+	@rm -f *.bits
+	@rm -f *.fasm
+	@rm -f *.frames*
+	@rm -f *.log
+	@rm -rf build
+
+.PHONY: all clean
+
+top.bit: $(VIVADO) $(SOURCES) top.xdc top.tcl
+	mkdir -p build
+	cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
+	cp build/*.bit ./
+
+top.fasm: top.bit
+	$(XRAY_BIT2FASM) --verbose $< > $@ \
+        || (rm -f top.fasm && exit 1)
+
+top.bits: top.bit
+	$(XRAY_BITREAD) -part_file $(XRAY_PART_YAML) -o top.bits -z -y top.bit
+
+segprint.log: top.bits
+	$(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log
+
+top.frames: top.fasm
+	$(XRAY_FASM2FRAMES) $< $@
+
+top.f2b.bit: top.frames
+	$(XRAY_DIR)/build/tools/xc7frames2bit --output_file $@ --part_name $(XRAY_PART) --part_file $(XRAY_PART_YAML) --frm_file $<
+
+program: top.f2b.bit
+	xc3sprog -c nexys4 top.f2b.bit

minitests/litex/min/arty/src.vivado/top.tcl

@@ -0,0 +1,28 @@
+create_project -force -name top -part $::env(XRAY_PART)
+set_msg_config -id {Common 17-55} -new_severity {Warning}
+read_verilog ../../verilog/VexRiscv_Lite.v
+read_verilog ../../verilog/top.v
+read_xdc ../top.xdc
+synth_design -directive default -top top -part $::env(XRAY_PART)
+report_timing_summary -file top_timing_synth.rpt
+report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
+report_utilization -file top_utilization_synth.rpt
+opt_design -directive default
+place_design -directive default
+report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
+report_utilization -file top_utilization_place.rpt
+report_io -file top_io.rpt
+report_control_sets -verbose -file top_control_sets.rpt
+report_clock_utilization -file top_clock_utilization.rpt
+route_design -directive default
+phys_opt_design -directive default
+report_timing_summary -no_header -no_detailed_paths
+write_checkpoint -force top_route.dcp
+report_route_status -file top_route_status.rpt
+report_drc -file top_drc.rpt
+report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
+report_power -file top_power.rpt
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+write_bitstream -force top.bit
+write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
+quit

minitests/litex/min/arty/src.vivado/top.xdc

@@ -0,0 +1,25 @@
+ ## serial:0.tx
+set_property LOC D10 [get_ports serial_tx]
+set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
+ ## serial:0.rx
+set_property LOC A9 [get_ports serial_rx]
+set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
+ ## cpu_reset:0
+set_property LOC C2 [get_ports cpu_reset]
+set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
+ ## clk100:0
+set_property LOC E3 [get_ports clk100]
+set_property IOSTANDARD LVCMOS33 [get_ports clk100]
+ ## eth_ref_clk:0
+set_property LOC G18 [get_ports eth_ref_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
+
+set_property INTERNAL_VREF 0.675 [get_iobanks 34]
+
+create_clock -name clk100 -period 10.0 [get_nets clk100]
+
+set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
+
+set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
+
+set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]

minitests/litex/min/arty/src.yosys/Makefile

@@ -0,0 +1,49 @@
+export XRAY_PART = xc7a35tcsg324-1
+export XRAY_PART_YAML = $(XRAY_DATABASE_DIR)/$(XRAY_DATABASE)/$(XRAY_PART).yaml
+YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
+SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/mem_2.init ../verilog/top.v ../verilog/VexRiscv_Lite.v
+
+all: top.f2b.bit
+
+clean:
+	@rm -f *.bit
+	@rm -f *.bin
+	@rm -f *.bits
+	@rm -f *.fasm
+	@rm -f *.frames*
+	@rm -f *.log
+	@rm -f *.edif
+	@rm -rf build
+
+.PHONY: all clean
+
+$(YOSYS):
+	cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc)
+
+top.edif: $(YOSYS) synth.ys $(SOURCES)
+	$(YOSYS) -s synth.ys -l yosys.log
+
+top.bit: $(VIVADO) top.edif top.xdc top.tcl
+	mkdir -p build
+	cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
+	python3 $(XRAY_DIR)/minitests/timing/clean_json5.py < build/iobuf_report.json5 > build/iobuf_report.json
+	cp build/*.bit ./
+
+top.fasm: top.bit
+	$(XRAY_BIT2FASM) --verbose $< > $@ \
+        || (rm -f top.fasm && exit 1)
+
+top.bits: top.bit
+	$(XRAY_BITREAD) -part_file $(XRAY_PART_YAML) -o top.bits -z -y top.bit
+
+segprint.log: top.bits
+	$(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log
+
+top.frames: top.fasm
+	$(XRAY_FASM2FRAMES) $< $@
+
+top.f2b.bit: top.frames
+	$(XRAY_DIR)/build/tools/xc7frames2bit --output_file $@ --part_name $(XRAY_PART) --part_file $(XRAY_PART_YAML) --frm_file $<
+
+program: top.f2b.bit
+	xc3sprog -c nexys4 top.f2b.bit

minitests/litex/min/arty/src.yosys/mem.init

@@ -0,0 +1 @@
+../verilog/mem.init

minitests/litex/min/arty/src.yosys/mem_1.init

@@ -0,0 +1 @@
+../verilog/mem_1.init

minitests/litex/min/arty/src.yosys/mem_2.init

@@ -0,0 +1 @@
+../verilog/mem_2.init

minitests/litex/min/arty/src.yosys/synth.ys

@@ -0,0 +1,3 @@
+read_verilog ../verilog/top.v
+read_verilog ../verilog/VexRiscv_Lite.v
+synth_xilinx -edif top.edif

minitests/litex/min/arty/src.yosys/top.tcl

@@ -0,0 +1,57 @@
+proc write_iobuf_report {filename} {
+    set fp [open $filename w]
+    puts $fp "{ \"tiles\": \["
+        foreach port [get_ports] {
+            set net [get_nets -of $port]
+            if { $net == "" } {
+                continue
+            }
+
+            set cell [get_cells -of $net]
+            set site [get_sites -of $cell]
+            set tile [get_tiles -of $site]
+
+            puts $fp "{"
+                puts $fp "\"port\": \"$port\","
+                puts $fp "\"pad_wire\": \"$net\","
+                puts $fp "\"cell\": \"$cell\","
+                puts $fp "\"site\": \"$site\","
+                puts $fp "\"tile\": \"$tile\","
+                puts $fp "\"type\": \"[get_property REF_NAME $cell]\","
+                puts $fp "\"IOSTANDARD\": \"\\\"[get_property IOSTANDARD $cell]\\\"\","
+                puts $fp "\"PULLTYPE\": \"\\\"[get_property PULLTYPE $cell]\\\"\","
+                puts $fp "\"DRIVE\": \"[get_property DRIVE $cell]\","
+                puts $fp "\"SLEW\": \"\\\"[get_property SLEW $cell]\\\"\","
+            puts $fp "},"
+        }
+    puts $fp "\]}"
+    close $fp
+}
+
+create_project -force -name top -part $::env(XRAY_PART)
+read_xdc ../top.xdc
+read_edif ../top.edif
+link_design -top top -part $::env(XRAY_PART)
+report_timing_summary -file top_timing_synth.rpt
+report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
+report_utilization -file top_utilization_synth.rpt
+opt_design
+place_design
+report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
+report_utilization -file top_utilization_place.rpt
+report_io -file top_io.rpt
+report_control_sets -verbose -file top_control_sets.rpt
+report_clock_utilization -file top_clock_utilization.rpt
+route_design
+phys_opt_design
+report_timing_summary -no_header -no_detailed_paths
+write_checkpoint -force top_route.dcp
+report_route_status -file top_route_status.rpt
+report_drc -file top_drc.rpt
+report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
+report_power -file top_power.rpt
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+write_bitstream -force top.bit
+write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
+write_iobuf_report iobuf_report.json5
+quit

minitests/litex/min/arty/src.yosys/top.xdc

@@ -0,0 +1,25 @@
+ ## serial:0.tx
+set_property LOC D10 [get_ports serial_tx]
+set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
+ ## serial:0.rx
+set_property LOC A9 [get_ports serial_rx]
+set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
+ ## cpu_reset:0
+set_property LOC C2 [get_ports cpu_reset]
+set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
+ ## clk100:0
+set_property LOC E3 [get_ports clk100]
+set_property IOSTANDARD LVCMOS33 [get_ports clk100]
+ ## eth_ref_clk:0
+set_property LOC G18 [get_ports eth_ref_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
+
+set_property INTERNAL_VREF 0.675 [get_iobanks 34]
+
+create_clock -name clk100 -period 10.0 [get_nets clk100]
+
+set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
+
+set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
+
+set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]

minitests/litex/min/arty/verilog/mem_2.init

@@ -0,0 +1,10 @@
+4d
+69
+6e
+69
+4c
+69
+74
+65
+78
+0