mirror of https://github.com/openXC7/prjxray.git
ddr-uart: using same design needed in arch-defs for the ddr test
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
fb5a88a6b8
commit
2f25a2682c
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@ -20,9 +20,63 @@ module top(
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output ddram_clk_n,
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output ddram_cke,
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output ddram_odt,
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output ddram_reset_n
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output ddram_reset_n,
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output [3:0] led
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);
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wire [3:0] led;
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assign led[0] = main_locked;
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assign led[1] = idelayctl_rdy;
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assign led[2] = 0;
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assign led[3] = 0;
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// Manually inserted OBUFs
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wire [13:0] ddram_a_iob;
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wire [ 2:0] ddram_ba_iob;
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wire ddram_ras_n_iob;
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wire ddram_cas_n_iob;
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wire ddram_we_n_iob;
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wire ddram_cs_n_iob;
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wire [ 1:0] ddram_dm_iob;
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wire ddram_cke_iob;
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wire ddram_odt_iob;
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wire ddram_reset_n_iob;
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a0 (.I(ddram_a_iob[ 0]), .O(ddram_a[ 0]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a1 (.I(ddram_a_iob[ 1]), .O(ddram_a[ 1]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a2 (.I(ddram_a_iob[ 2]), .O(ddram_a[ 2]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a3 (.I(ddram_a_iob[ 3]), .O(ddram_a[ 3]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a4 (.I(ddram_a_iob[ 4]), .O(ddram_a[ 4]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a5 (.I(ddram_a_iob[ 5]), .O(ddram_a[ 5]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a6 (.I(ddram_a_iob[ 6]), .O(ddram_a[ 6]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a7 (.I(ddram_a_iob[ 7]), .O(ddram_a[ 7]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a8 (.I(ddram_a_iob[ 8]), .O(ddram_a[ 8]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a9 (.I(ddram_a_iob[ 9]), .O(ddram_a[ 9]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a10 (.I(ddram_a_iob[10]), .O(ddram_a[10]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a11 (.I(ddram_a_iob[11]), .O(ddram_a[11]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a12 (.I(ddram_a_iob[12]), .O(ddram_a[12]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a13 (.I(ddram_a_iob[13]), .O(ddram_a[13]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ba0 (.I(ddram_ba_iob[0]), .O(ddram_ba[0]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ba1 (.I(ddram_ba_iob[1]), .O(ddram_ba[1]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ba2 (.I(ddram_ba_iob[2]), .O(ddram_ba[2]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_dm0 (.I(ddram_dm_iob[0]), .O(ddram_dm[0]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_dm1 (.I(ddram_dm_iob[1]), .O(ddram_dm[1]));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ras (.I(ddram_ras_n_iob), .O(ddram_ras_n));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_cas (.I(ddram_cas_n_iob), .O(ddram_cas_n));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_we (.I(ddram_we_n_iob), .O(ddram_we_n));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_cs (.I(ddram_cs_n_iob), .O(ddram_cs_n));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_cke (.I(ddram_cke_iob), .O(ddram_cke));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_odt (.I(ddram_odt_iob), .O(ddram_odt));
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OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_rst (.I(ddram_reset_n_iob),.O(ddram_reset_n));
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// End manually inserted OBUFs
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wire idelayctl_rdy;
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reg main_ctrl_reset_storage = 1'd0;
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reg main_ctrl_reset_re = 1'd0;
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reg [31:0] main_ctrl_scratch_storage = 32'd305419896;
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@ -154,12 +208,13 @@ reg main_interface0_wb_sdram_err = 1'd0;
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wire sys_clk;
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wire sys_rst;
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wire sys4x_clk;
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wire sys4x_clkb;
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wire sys4x_dqs_clk;
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wire clk200_clk;
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wire clk200_rst;
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wire main_reset;
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wire main_locked;
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wire main_clkin;
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wire main_pll_clkin;
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wire main_clkout0;
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wire main_clkout_buf0;
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wire main_clkout1;
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@ -168,6 +223,7 @@ wire main_clkout2;
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wire main_clkout_buf2;
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wire main_clkout3;
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wire main_clkout_buf3;
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wire main_clkout_buf4;
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reg [3:0] main_reset_counter = 4'd15;
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reg main_ic_reset = 1'd1;
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reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd16;
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@ -2388,9 +2444,9 @@ always @(*) begin
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endcase
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end
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assign main_reset = (~cpu_reset);
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assign main_clkin = clk100;
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assign sys_clk = main_clkout_buf0;
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assign sys4x_clk = main_clkout_buf1;
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assign sys4x_clkb = main_clkout_buf4;
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assign sys4x_dqs_clk = main_clkout_buf2;
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assign clk200_clk = main_clkout_buf3;
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always @(*) begin
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@ -9652,31 +9708,51 @@ initial begin
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$readmemh("mem_1.init", mem_1);
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end
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(* LOC="BUFGCTRL_X0Y16" *)
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BUFG BUFG(
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.I(clk100),
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.O(main_pll_clkin)
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);
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(* LOC="BUFGCTRL_X0Y0" *)
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BUFG BUFG_1(
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.I(main_clkout0),
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.O(main_clkout_buf0)
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);
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BUFG BUFG_1(
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(* LOC="BUFGCTRL_X0Y1" *)
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BUFG BUFG_2(
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.I(main_clkout1),
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.O(main_clkout_buf1)
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);
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BUFG BUFG_2(
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(* LOC="BUFGCTRL_X0Y3" *)
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BUFG BUFG_3(
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.I(main_clkout2),
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.O(main_clkout_buf2)
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);
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BUFG BUFG_3(
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(* LOC="BUFGCTRL_X0Y2" *)
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BUFG BUFG_4(
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.I(main_clkout3),
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.O(main_clkout_buf3)
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);
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(* LOC="BUFGCTRL_X0Y4" *)
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BUFG BUFG_5(
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.I((~main_clkout_buf1)),
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.O(main_clkout_buf4)
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);
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(* LOC="IDELAYCTRL_X1Y0" *)
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IDELAYCTRL IDELAYCTRL(
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.REFCLK(clk200_clk),
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.RST(main_ic_reset)
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.RST(main_ic_reset),
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.RDY(idelayctl_rdy)
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);
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wire tq;
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OSERDESE2 #(
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.DATA_RATE_OQ("DDR"),
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.DATA_RATE_TQ("BUF"),
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@ -9696,13 +9772,17 @@ OSERDESE2 #(
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.D8(1'd1),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(main_a7ddrphy_sd_clk_se_nodelay)
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.OQ(main_a7ddrphy_sd_clk_se_nodelay),
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.TQ(tq),
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.TCE(1'd1),
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.T1(1'b0)
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);
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OBUFDS OBUFDS(
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OBUFTDS OBUFTDS_2(
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.I(main_a7ddrphy_sd_clk_se_nodelay),
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.O(ddram_clk_p),
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.OB(ddram_clk_n)
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.OB(ddram_clk_n),
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.T(tq)
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);
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OSERDESE2 #(
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@ -9724,7 +9804,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[0]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[0])
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.OQ(ddram_a_iob[0])
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);
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OSERDESE2 #(
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@ -9746,7 +9826,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[1]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[1])
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.OQ(ddram_a_iob[1])
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);
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OSERDESE2 #(
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@ -9768,7 +9848,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[2]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[2])
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.OQ(ddram_a_iob[2])
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);
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OSERDESE2 #(
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@ -9790,7 +9870,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[3]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[3])
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.OQ(ddram_a_iob[3])
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);
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OSERDESE2 #(
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@ -9812,7 +9892,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[4]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[4])
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.OQ(ddram_a_iob[4])
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);
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OSERDESE2 #(
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@ -9834,7 +9914,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[5]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[5])
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.OQ(ddram_a_iob[5])
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);
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OSERDESE2 #(
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@ -9856,7 +9936,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[6]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[6])
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.OQ(ddram_a_iob[6])
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);
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OSERDESE2 #(
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@ -9878,7 +9958,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[7]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[7])
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.OQ(ddram_a_iob[7])
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);
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OSERDESE2 #(
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@ -9900,7 +9980,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[8]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[8])
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.OQ(ddram_a_iob[8])
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);
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OSERDESE2 #(
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@ -9922,7 +10002,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[9]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[9])
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.OQ(ddram_a_iob[9])
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);
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OSERDESE2 #(
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@ -9944,7 +10024,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[10]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[10])
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.OQ(ddram_a_iob[10])
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);
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OSERDESE2 #(
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@ -9966,7 +10046,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[11]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[11])
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.OQ(ddram_a_iob[11])
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);
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OSERDESE2 #(
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@ -9988,7 +10068,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[12]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[12])
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.OQ(ddram_a_iob[12])
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);
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OSERDESE2 #(
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@ -10010,7 +10090,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_address[13]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_a[13])
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.OQ(ddram_a_iob[13])
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);
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OSERDESE2 #(
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@ -10032,7 +10112,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_bank[0]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_ba[0])
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.OQ(ddram_ba_iob[0])
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);
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OSERDESE2 #(
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@ -10054,7 +10134,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_bank[1]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_ba[1])
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.OQ(ddram_ba_iob[1])
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);
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OSERDESE2 #(
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@ -10076,7 +10156,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_bank[2]),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_ba[2])
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.OQ(ddram_ba_iob[2])
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);
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OSERDESE2 #(
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@ -10098,7 +10178,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_ras_n),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_ras_n)
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.OQ(ddram_ras_n_iob)
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);
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OSERDESE2 #(
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@ -10120,7 +10200,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_cas_n),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_cas_n)
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.OQ(ddram_cas_n_iob)
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);
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OSERDESE2 #(
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@ -10142,7 +10222,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_we_n),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_we_n)
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.OQ(ddram_we_n_iob)
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);
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OSERDESE2 #(
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@ -10164,7 +10244,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_cke),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_cke)
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.OQ(ddram_cke_iob)
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);
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OSERDESE2 #(
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@ -10186,7 +10266,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_odt),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_odt)
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.OQ(ddram_odt_iob)
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);
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OSERDESE2 #(
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@ -10208,7 +10288,7 @@ OSERDESE2 #(
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.D8(main_a7ddrphy_dfi_p3_reset_n),
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.OCE(1'd1),
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.RST(sys_rst),
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.OQ(ddram_reset_n)
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.OQ(ddram_reset_n_iob)
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);
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OSERDESE2 #(
|
||||
|
|
@ -10230,7 +10310,7 @@ OSERDESE2 #(
|
|||
.D8(main_a7ddrphy_dfi_p3_cs_n),
|
||||
.OCE(1'd1),
|
||||
.RST(sys_rst),
|
||||
.OQ(ddram_cs_n)
|
||||
.OQ(ddram_cs_n_iob)
|
||||
);
|
||||
|
||||
OSERDESE2 #(
|
||||
|
|
@ -10252,7 +10332,7 @@ OSERDESE2 #(
|
|||
.D8(main_a7ddrphy_dfi_p3_wrdata_mask[2]),
|
||||
.OCE(1'd1),
|
||||
.RST(sys_rst),
|
||||
.OQ(ddram_dm[0])
|
||||
.OQ(ddram_dm_iob[0])
|
||||
);
|
||||
|
||||
OSERDESE2 #(
|
||||
|
|
@ -10307,7 +10387,7 @@ OSERDESE2 #(
|
|||
.D8(main_a7ddrphy_dfi_p3_wrdata_mask[3]),
|
||||
.OCE(1'd1),
|
||||
.RST(sys_rst),
|
||||
.OQ(ddram_dm[1])
|
||||
.OQ(ddram_dm_iob[1])
|
||||
);
|
||||
|
||||
OSERDESE2 #(
|
||||
|
|
@ -10379,7 +10459,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed0),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -10455,7 +10535,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed1),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -10531,7 +10611,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed2),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -10607,7 +10687,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed3),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -10683,7 +10763,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed4),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -10759,7 +10839,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed5),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -10835,7 +10915,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed6),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -10911,7 +10991,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed7),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -10987,7 +11067,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed8),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -11063,7 +11143,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed9),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -11139,7 +11219,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed10),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -11215,7 +11295,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed11),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -11291,7 +11371,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed12),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -11367,7 +11447,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed13),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -11443,7 +11523,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed14),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -11519,7 +11599,7 @@ ISERDESE2 #(
|
|||
.BITSLIP(1'd0),
|
||||
.CE1(1'd1),
|
||||
.CLK(sys4x_clk),
|
||||
.CLKB((~sys4x_clk)),
|
||||
.CLKB(sys4x_clkb),
|
||||
.CLKDIV(sys_clk),
|
||||
.DDLY(main_a7ddrphy_dq_i_delayed15),
|
||||
.RST(sys_rst),
|
||||
|
|
@ -11681,6 +11761,7 @@ end
|
|||
|
||||
assign main_tag_port_dat_r = tag_mem[memadr_2];
|
||||
|
||||
(* LOC="PLLE2_ADV_X1Y0" *)
|
||||
PLLE2_ADV #(
|
||||
.CLKFBOUT_MULT(5'd16),
|
||||
.CLKIN1_PERIOD(10.0),
|
||||
|
|
@ -11697,7 +11778,7 @@ PLLE2_ADV #(
|
|||
.STARTUP_WAIT("FALSE")
|
||||
) PLLE2_ADV (
|
||||
.CLKFBIN(builder_pll_fb),
|
||||
.CLKIN1(main_clkin),
|
||||
.CLKIN1(main_pll_clkin),
|
||||
.RST(main_reset),
|
||||
.CLKFBOUT(builder_pll_fb),
|
||||
.CLKOUT0(main_clkout0),
|
||||
|
|
|
|||
|
|
@ -17,6 +17,22 @@ set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
|
|||
set_property LOC E3 [get_ports clk100]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk100]
|
||||
|
||||
# led[0]
|
||||
set_property LOC H5 [get_ports led[0]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
|
||||
|
||||
# led[1]
|
||||
set_property LOC J5 [get_ports led[1]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
|
||||
|
||||
# led[2]
|
||||
set_property LOC T9 [get_ports led[2]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
|
||||
|
||||
# led[3]
|
||||
set_property LOC T10 [get_ports led[3]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC R2 [get_ports ddram_a[0]]
|
||||
set_property SLEW FAST [get_ports ddram_a[0]]
|
||||
|
|
@ -295,4 +311,4 @@ set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
|
|||
|
||||
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
|
|
|
|||
Loading…
Reference in New Issue